Modules
	CMSIS Global Defines
	IO Type Qualifiers are used

	Defines and Type Definitions
	Type definitions and defines for Cortex-M processor based devices.

#define	__CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)

#define	__CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)

#define	__CM0_CMSIS_VERSION

#define	__CORTEX_M (0U)

#define	__FPU_USED 0U

#define	__CORE_CM0_H_DEPENDANT

#define	__I volatile const

#define	__O volatile

#define	__IO volatile

#define	__IM volatile const /! Defines 'read only' structure member permissions /

#define	__OM volatile /! Defines 'write only' structure member permissions /

#define	__IOM volatile /! Defines 'read / write' structure member permissions /

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

Detailed Description

MISRA-C:2004 Compliance Exceptions

CMSIS violates the following MISRA-C:2004 rules:

Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'.

Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers.

Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code.

Macro Definition Documentation

◆ __CM0_CMSIS_VERSION

#define __CM0_CMSIS_VERSION

Value:

((__CM0_CMSIS_VERSION_MAIN << 16U) | \

__CM0_CMSIS_VERSION_SUB )

Deprecated:: CMSIS HAL version number

◆ __CM0_CMSIS_VERSION_MAIN

#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)

Deprecated:: [31:16] CMSIS HAL main version

◆ __CM0_CMSIS_VERSION_SUB

#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)

Deprecated:: [15:0] CMSIS HAL sub version

◆ __CORE_CM0_H_DEPENDANT

#define __CORE_CM0_H_DEPENDANT

Deprecated:: [31:16] CMSIS HAL main version

◆ __CORTEX_M

#define __CORTEX_M (0U)

Cortex-M Core

◆ __FPU_USED

#define __FPU_USED 0U

__FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all

◆ __I

#define __I volatile const

Defines 'read only' permissions

◆ __IM

#define __IM volatile const /*! Defines 'read only' structure member permissions */

Deprecated:: [31:16] CMSIS HAL main version

◆ __IO

#define __IO volatile

Defines 'read / write' permissions

◆ __IOM

#define __IOM volatile /*! Defines 'read / write' structure member permissions */

Deprecated:: [31:16] CMSIS HAL main version

◆ __O

#define __O volatile

Defines 'write only' permissions

◆ __OM

#define __OM volatile /*! Defines 'write only' structure member permissions */

Deprecated:: [31:16] CMSIS HAL main version

◆ APSR_C_Msk

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Pos

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_N_Msk

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Pos

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_V_Msk

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Pos

#define APSR_V_Pos 28U

APSR: V Position

◆ APSR_Z_Msk

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Pos

#define APSR_Z_Pos 30U

APSR: Z Position

◆ CONTROL_SPSEL_Msk

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Pos

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

◆ IPSR_ISR_Msk

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Pos

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

◆ xPSR_C_Msk

#define xPSR_C_Msk (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Pos

#define xPSR_C_Pos 29U

xPSR: C Position

◆ xPSR_ISR_Msk

#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Pos

#define xPSR_ISR_Pos 0U

xPSR: ISR Position

◆ xPSR_N_Msk

#define xPSR_N_Msk (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Pos

#define xPSR_N_Pos 31U

xPSR: N Position

◆ xPSR_T_Msk

#define xPSR_T_Msk (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Pos

#define xPSR_T_Pos 24U

xPSR: T Position

◆ xPSR_V_Msk

#define xPSR_V_Msk (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Pos

#define xPSR_V_Pos 28U

xPSR: V Position

◆ xPSR_Z_Msk

#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Pos

#define xPSR_Z_Pos 30U

xPSR: Z Position

Modules