hw_pdc.h

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#ifndef HW_PDC_H_
#define HW_PDC_H_
 
#if dg_configUSE_HW_PDC
 
#include <sdk_defs.h>
 
#define PDC_IRQn PDC_M33_IRQn
 
#define HW_PDC_LUT_SIZE                 (12)
#define HW_PDC_INVALID_LUT_INDEX        (0xFFFF)
#define HW_PDC_UNUSED_LUT_ENTRY_VALUE   (0UL)
#define HW_PDC_FILTER_DONT_CARE         (0xFF)
 
typedef enum {
        HW_PDC_TRIG_SELECT_P0_GPIO      = 0, 
        HW_PDC_TRIG_SELECT_P1_GPIO      = 1, 
        HW_PDC_TRIG_SELECT_PERIPHERAL   = 2, 
        HW_PDC_TRIG_SELECT_MASTER       = 3, 
} HW_PDC_TRIG_SELECT;
 
typedef enum {
        HW_PDC_PERIPH_TRIG_ID_TIMER             = 0x0, 
        HW_PDC_PERIPH_TRIG_ID_TIMER2            = 0x1, 
        HW_PDC_PERIPH_TRIG_ID_TIMER3_QDEC       = 0x2, 
        HW_PDC_PERIPH_TRIG_ID_TIMER4            = 0x3, 
        HW_PDC_PERIPH_TRIG_ID_RTC_ALARM         = 0x4, 
        HW_PDC_PERIPH_TRIG_ID_RTC_TIMER         = 0x5, 
        HW_PDC_PERIPH_TRIG_ID_MAC_TIMER         = 0x6, 
        HW_PDC_PERIPH_TRIG_ID_XTAL32MRDY        = 0x8, 
        HW_PDC_PERIPH_TRIG_ID_RFDIAG            = 0x9, 
        HW_PDC_PERIPH_TRIG_ID_COMBO             = 0xA, 
        HW_PDC_PERIPH_TRIG_ID_FCU_IRQ           = 0xC, 
        HW_PDC_PERIPH_TRIG_ID_FAST_WKUP         = 0xD, 
        HW_PDC_PERIPH_TRIG_ID_MASTERONLY        = 0xF, 
} HW_PDC_PERIPH_TRIG_ID;
 
typedef enum {
        HW_PDC_MASTER_INVALID   = 0, 
        HW_PDC_MASTER_CM33      = 1, 
        HW_PDC_MASTER_CMAC      = 2, 
} HW_PDC_MASTER;
 
typedef enum {
        HW_PDC_LUT_ENTRY_EN_COM  = PDC_PDC_CTRL0_REG_EN_COM_Msk, 
        HW_PDC_LUT_ENTRY_EN_PER  = PDC_PDC_CTRL0_REG_EN_PER_Msk, 
        HW_PDC_LUT_ENTRY_EN_TMR  = PDC_PDC_CTRL0_REG_EN_TMR_Msk, 
        HW_PDC_LUT_ENTRY_EN_XTAL = PDC_PDC_CTRL0_REG_EN_XTAL_Msk, 
} HW_PDC_LUT_ENTRY_EN;
 
typedef enum {
        HW_PDC_ERROR_NONE = 0,
        HW_PDC_ERROR_INVALID_LUT_ENTRY,
        HW_PDC_ERROR_INVALID_PARAM
} HW_PDC_ERROR;
 
typedef struct {
        HW_PDC_TRIG_SELECT      trig_select;    
        HW_PDC_PERIPH_TRIG_ID   trig_id;        
        HW_PDC_MASTER           wakeup_master;  
        HW_PDC_LUT_ENTRY_EN     flags;          
} hw_pdc_entry_t;
 
typedef enum {
        HW_PDC_RESET_BLOCKED_TRIGGERS = 0,                                                      
        HW_PDC_PD_SYS_BLOCKED = REG_MSK(PDC, PDC_CONFIG_REG, PD_SYS_WKUP_CONFIG),               
        HW_PDC_PD_RAD_BLOCKED = REG_MSK(PDC, PDC_CONFIG_REG, PD_RAD_WKUP_CONFIG),               
        HW_PDC_ALL_BLOCKED_EXCEPT_FCU = REG_MSK(PDC, PDC_CONFIG_REG, TRIG_SELECT_CONFIG),       
} HW_PDC_BLOCKED_TRIG;
 
typedef struct {
        uint8_t num;          
        hw_pdc_entry_t* keep; 
} hw_pdc_lut_keep_t;
 
#define HW_PDC_LUT_ENTRY_FIELD_MASK(field) \
        (PDC_PDC_CTRL0_REG_##field##_Msk)
 
#define HW_PDC_LUT_ENTRY_FIELD_POS(field) \
        (PDC_PDC_CTRL0_REG_##field##_Pos)
 
#define HW_PDC_LUT_ENTRY_FIELD_VAL(field, val) \
        (((val) << HW_PDC_LUT_ENTRY_FIELD_POS(field)) & HW_PDC_LUT_ENTRY_FIELD_MASK(field))
 
#define HW_PDC_LUT_ENTRY_VAL(trig_select, trig_id, wakeup_master, flags)        \
                (                                                               \
                    HW_PDC_LUT_ENTRY_FIELD_VAL(TRIG_SELECT, trig_select)        \
                  | HW_PDC_LUT_ENTRY_FIELD_VAL(TRIG_ID,     trig_id)            \
                  | HW_PDC_LUT_ENTRY_FIELD_VAL(PDC_MASTER,  wakeup_master)      \
                  | flags                                                       \
                )
 
/*
 * Shorthand macros
 */
#define HW_PDC_TRIGGER_FROM_PORT0(pin, wakeup_master, flags) \
        HW_PDC_LUT_ENTRY_VAL(HW_PDC_TRIG_SELECT_P0_GPIO, pin, wakeup_master, flags)
 
#define HW_PDC_TRIGGER_FROM_PORT1(pin, wakeup_master, flags) \
        HW_PDC_LUT_ENTRY_VAL(HW_PDC_TRIG_SELECT_P1_GPIO, pin, wakeup_master, flags)
 
#define HW_PDC_TRIGGER_FROM_PERIPH(peripheral, wakeup_master, flags) \
        HW_PDC_LUT_ENTRY_VAL(HW_PDC_TRIG_SELECT_PERIPHERAL, peripheral, wakeup_master, flags)
 
#define HW_PDC_TRIGGER_FROM_MASTER(wakeup_master, flags) \
        HW_PDC_LUT_ENTRY_VAL(HW_PDC_TRIG_SELECT_MASTER, HW_PDC_PERIPH_TRIG_ID_MASTERONLY, \
                                wakeup_master, flags)
 
__STATIC_INLINE uint32_t hw_pdc_read_entry(uint32_t idx)
{
        ASSERT_ERROR(idx < HW_PDC_LUT_SIZE);
 
        return *(&PDC->PDC_CTRL0_REG + idx);
}
 
__RETAINED_CODE uint32_t hw_pdc_add_entry(uint32_t lut_entry);
 
uint32_t hw_pdc_remove_entry(uint32_t idx);
 
__STATIC_INLINE uint32_t hw_pdc_get_pending(void)
{
        return PDC->PDC_PENDING_REG;
}
 
__STATIC_INLINE uint32_t hw_pdc_get_pending_cm33(void)
{
        return PDC->PDC_PENDING_CM33_REG;
}
 
__STATIC_INLINE uint32_t hw_pdc_get_pending_cmac(void)
{
        return PDC->PDC_PENDING_CMAC_REG;
}
 
 
__STATIC_INLINE void hw_pdc_acknowledge(uint32_t idx)
{
        ASSERT_ERROR(idx < HW_PDC_LUT_SIZE);
 
        PDC->PDC_ACKNOWLEDGE_REG= idx;
}
 
void hw_pdc_write_entry(uint32_t idx, uint32_t value);
 
__STATIC_INLINE HW_PDC_ERROR hw_pdc_set_pending(uint32_t idx)
{
        if (idx >= HW_PDC_LUT_SIZE) {
                return HW_PDC_ERROR_INVALID_PARAM;
        }
 
        if ((hw_pdc_read_entry(idx) & HW_PDC_LUT_ENTRY_FIELD_MASK(PDC_MASTER)) == 0) {
                return HW_PDC_ERROR_INVALID_LUT_ENTRY;
        }
 
        PDC->PDC_SET_PENDING_REG = idx;
 
        return HW_PDC_ERROR_NONE;
}
 
__STATIC_FORCEINLINE bool hw_pdc_is_pending(uint32_t idx)
{
        ASSERT_ERROR(idx < HW_PDC_LUT_SIZE);
 
        return !!(PDC->PDC_PENDING_REG & (1 << idx));
}
 
void hw_pdc_ack_all_pending_cm33(void);
 
void hw_pdc_lut_reset(void);
 
void hw_pdc_lut_keep(hw_pdc_lut_keep_t* keep);
 
uint32_t hw_pdc_find_entry(uint32_t trig_select, uint32_t trig_id,
                             uint32_t wakeup_master, uint32_t flags, uint32_t start);
__STATIC_FORCEINLINE void hw_pdc_set_blocked_triggers(HW_PDC_BLOCKED_TRIG blocked)
{
        PDC->PDC_CONFIG_REG = blocked;
}
 
__STATIC_FORCEINLINE HW_PDC_BLOCKED_TRIG hw_pdc_get_blocked_triggers()
{
        return PDC->PDC_CONFIG_REG;
}
 
#endif /* dg_configUSE_HW_PDC */
#endif /* HW_PDC_H_ */