QSPIC Erase instruction configuration structure (auto access mode) More...

#include <hw_qspi_v2.h>

Data Fields
HW_QSPI_BUS_MODE	opcode_bus_mode: 2

HW_QSPI_BUS_MODE	addr_bus_mode: 2

uint32_t	hclk_cycles: 4

uint8_t	opcode

uint16_t	cs_idle_delay_nsec

Detailed Description

QSPIC Erase instruction configuration structure (auto access mode)

Field Documentation

◆ addr_bus_mode

HW_QSPI_BUS_MODE hw_qspi_erase_instr_config_t::addr_bus_mode

Bus mode of the address phase

◆ cs_idle_delay_nsec

uint16_t hw_qspi_erase_instr_config_t::cs_idle_delay_nsec

The minimum CS idle delay in nsec between a Write Enable, Erase, Erase Suspend or Erase Resume command and the next consecutive command

◆ hclk_cycles

uint32_t hw_qspi_erase_instr_config_t::hclk_cycles

The number of AMBA AHB hclk cycles (0..15) without memory read requests before executing an erase or erase resume command. Use this setting to delay one of the aforementioned commands otherwise keep it 0.

◆ opcode

uint8_t hw_qspi_erase_instr_config_t::opcode

Erase command opcode

◆ opcode_bus_mode

HW_QSPI_BUS_MODE hw_qspi_erase_instr_config_t::opcode_bus_mode

Bus mode of the opcode phase

The documentation for this struct was generated from the following file:

sdk/bsp/peripherals/include/hw_qspi_v2.h