hw_uart.h

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#ifndef HW_UART_H_
#define HW_UART_H_
 
#if dg_configUSE_HW_UART
 
#include <stdbool.h>
#include <stdint.h>
#include "sdk_defs.h"
 
#define UBA(id)         ((UART2_Type *)id)
#define HW_UART1        ((uint16_t *)UART_BASE)
#define HW_UART2        ((uint16_t *)UART2_BASE)
typedef uint16_t * HW_UART_ID;
 
#define HW_UART_REG_FIELD_MASK(instance, reg, field) \
        (UART##instance##_UART##instance##_##reg##_REG_##field##_Msk)
 
#define HW_UART_REG_FIELD_POS(instance, reg, field) \
        (UART##instance##_UART##instance##_##reg##_REG_##field##_Pos)
 
#define HW_UART_REG_GETF(id, reg, field) \
                ((UBA(id)->UART2_##reg##_REG & (UART2_UART2_##reg##_REG_##field##_Msk)) >> (UART2_UART2_##reg##_REG_##field##_Pos))
 
#define HW_UART_REG_SETF(id, reg, field, new_val) \
                UBA(id)->UART2_##reg##_REG = ((UBA(id)->UART2_##reg##_REG & ~(UART2_UART2_##reg##_REG_##field##_Msk)) | \
                ((UART2_UART2_##reg##_REG_##field##_Msk) & ((new_val) << (UART2_UART2_##reg##_REG_##field##_Pos))))
 
#define HW_UART_DMA_SUPPORT             dg_configUART_DMA_SUPPORT
 
#if (HW_UART_DMA_SUPPORT == 1)
#include "hw_dma.h"
 
typedef hw_dma_periph_prio_t hw_uart_dma_prio_t;
#endif /* HW_UART_DMA_SUPPORT */
 
/*
 * ENUMERATION DEFINITIONS
 *****************************************************************************************
 */
 
typedef enum {
        HW_UART_INT_MODEM_STAT         = 0,
        HW_UART_INT_NO_INT_PEND        = 1,
        HW_UART_INT_THR_EMPTY          = 2,
        HW_UART_INT_RECEIVED_AVAILABLE = 4,
        HW_UART_INT_RECEIVE_LINE_STAT  = 6,
        HW_UART_INT_BUSY_DETECTED      = 7,
        HW_UART_INT_TIMEOUT            = 12,
} HW_UART_INT;
 
typedef enum {
        HW_UART_BAUDRATE_1200           = 0,    
        HW_UART_BAUDRATE_2400           = 1,    
        HW_UART_BAUDRATE_4800           = 2,    
        HW_UART_BAUDRATE_9600           = 3,    
        HW_UART_BAUDRATE_14400          = 4,    
        HW_UART_BAUDRATE_19200          = 5,    
        HW_UART_BAUDRATE_28800          = 6,    
        HW_UART_BAUDRATE_38400          = 7,    
        HW_UART_BAUDRATE_57600          = 8,    
        HW_UART_BAUDRATE_115200         = 9,    
        HW_UART_BAUDRATE_230400         = 10,   
        HW_UART_BAUDRATE_256000         = 11,   
        HW_UART_BAUDRATE_460800         = 12,   
        HW_UART_BAUDRATE_500000         = 13,   
        HW_UART_BAUDRATE_921600         = 14,   
        HW_UART_BAUDRATE_1000000        = 15,   
        HW_UART_BAUDRATE_2000000        = 16,   
        HW_UART_BAUDRATE_3000000        = 17,   
        HW_UART_BAUDRATE_MAX                    
} HW_UART_BAUDRATE;
 
extern const uint32_t hw_uart_divisor[HW_UART_BAUDRATE_MAX];
 
typedef enum {
        HW_UART_DATABITS_5        = 0,
        HW_UART_DATABITS_6        = 1,
        HW_UART_DATABITS_7        = 2,
        HW_UART_DATABITS_8        = 3,
} HW_UART_DATABITS;
 
typedef enum {
        HW_UART_PARITY_NONE     = 0,
        HW_UART_PARITY_ODD      = 1,
        HW_UART_PARITY_EVEN     = 3,
} HW_UART_PARITY;
 
typedef enum {
        HW_UART_STOPBITS_1 = 0,
        HW_UART_STOPBITS_2 = 1,         
} HW_UART_STOPBITS;
 
typedef enum {
        HW_UART_ERR_NOERROR     = 0,
        HW_UART_ERR_OE          = 1,             
        HW_UART_ERR_PE          = 2,             
        HW_UART_ERR_FE          = 3,             
        HW_UART_ERR_BI          = 4,             
        HW_UART_ERR_RFE         = 5,             
} HW_UART_ERROR;
 
typedef enum {
        HW_UART_CONFIG_ERR_NOERR        = 0,
        HW_UART_CONFIG_ERR_RX_FIFO      = 1,         
        HW_UART_CONFIG_ERR_TX_FIFO      = 2,         
        HW_UART_CONFIG_ERR_RXTX_FIFO    = 3,         
        HW_UART_CONFIG_ERR_RX_SIZE      = 4,         
        HW_UART_CONFIG_ERR_TX_SIZE      = 5,         
} HW_UART_CONFIG_ERR;
 
typedef struct {
        // Baud rate divisor
        HW_UART_BAUDRATE        baud_rate;
        HW_UART_DATABITS        data:2;
        HW_UART_PARITY          parity:2;
        HW_UART_STOPBITS        stop:1;
        uint8_t                 auto_flow_control:1;
        uint8_t                 use_fifo:1;
        uint8_t                 tx_fifo_tr_lvl:2;
        uint8_t                 rx_fifo_tr_lvl:2;
#if (HW_UART_DMA_SUPPORT == 1)
        uint8_t                 use_dma:1;
        HW_DMA_CHANNEL          tx_dma_channel:4;
        HW_DMA_CHANNEL          rx_dma_channel:4;
        uint8_t                 tx_dma_burst_lvl:2; /* 0 no burst mode, 1 burst size of 4, 2 burst size of 8 */
        uint8_t                 rx_dma_burst_lvl:2; /* 0 no burst mode, 1 burst size of 4, 2 burst size of 8 */
        hw_uart_dma_prio_t      dma_prio;
#endif /* HW_UART_DMA_SUPPORT */
} uart_config;
 
#ifdef HW_UART_ENABLE_USER_ISR
 
typedef void (*hw_uart_interrupt_isr)(void);
 
void hw_uart_set_isr(HW_UART_ID uart, hw_uart_interrupt_isr isr);
#endif
 
typedef void (*hw_uart_tx_callback)(void *user_data, uint16_t written);
typedef void (*hw_uart_rx_callback)(void *user_data, uint16_t read);
typedef void (*hw_uart_err_callback)(void *user_data, HW_UART_ERROR error);
 
//======================= Status functions ====================================
 
__STATIC_INLINE bool hw_uart_is_busy(HW_UART_ID uart)
{
        return HW_UART_REG_GETF(uart, USR, UART_BUSY);
}
 
//===================== Read/Write functions ===================================
 
uint8_t hw_uart_read(HW_UART_ID uart);
 
void hw_uart_write(HW_UART_ID uart, uint8_t data);
 
uint16_t hw_uart_abort_receive(HW_UART_ID uart);
 
#if (dg_configUART_RX_CIRCULAR_DMA == 1)
 
uint16_t hw_uart_copy_dma_rx_to_user_buffer(HW_UART_ID uart);
#endif
 
uint16_t hw_uart_abort_send(HW_UART_ID uart);
 
uint16_t hw_uart_peek_received(HW_UART_ID uart);
 
uint16_t hw_uart_peek_transmitted(HW_UART_ID uart);
 
__STATIC_INLINE uint8_t hw_uart_rxdata_getf(HW_UART_ID uart)
{
        // Read element from the receive FIFO
        return UBA(uart)->UART2_RBR_THR_DLL_REG;
}
 
__STATIC_INLINE void hw_uart_txdata_setf(HW_UART_ID uart, uint8_t data)
{
        // Write data to the transmit FIFO
        UBA(uart)->UART2_RBR_THR_DLL_REG = data;
}
 
void hw_uart_write_buffer(HW_UART_ID uart, const void *data, uint16_t len);
 
HW_UART_CONFIG_ERR hw_uart_send(HW_UART_ID uart, const void *data, uint16_t len, hw_uart_tx_callback cb,
                                                                                void *user_data);
HW_UART_CONFIG_ERR hw_uart_receive(HW_UART_ID uart, void *data, uint16_t len, hw_uart_rx_callback cb,
                                                                                void *user_data);
void hw_uart_receive_error_checking(HW_UART_ID uart, void *data, uint16_t len, hw_uart_rx_callback cb,
                                            void *user_data, hw_uart_err_callback err_cb, void *error_data);
 
#if (HW_UART_DMA_SUPPORT == 1)
 
void hw_uart_configure_dma_channels(HW_UART_ID uart, const uart_config *uart_init);
 
#endif /* HW_UART_DMA_SUPPORT */
 
//============== Interrupt handling ============================================
 
__STATIC_INLINE void hw_uart_rec_data_int_set(HW_UART_ID uart, uint8_t recdataavail)
{
        // Set ERBFI bit in Interrupt Enable Register
        HW_UART_REG_SETF(uart, IER_DLH, ERBFI_DLH0, recdataavail);
}
__STATIC_INLINE void hw_uart_tx_empty_int_set(HW_UART_ID uart, uint8_t txempty)
{
        // Set ETBEI bit in Interrupt Enable Register
        HW_UART_REG_SETF(uart, IER_DLH, ETBEI_DLH1, txempty);
}
 
__STATIC_INLINE void hw_uart_linestat_int_set(HW_UART_ID uart, uint8_t linestat)
{
        // Set ELSI bit in Interrupt Enable Register
        HW_UART_REG_SETF(uart, IER_DLH, ELSI_DLH2, linestat);
}
 
__STATIC_INLINE void hw_uart_pthre_int_set(HW_UART_ID uart, uint8_t pthre)
{
        // Set PTIME bit in Interrupt Enable Register
        HW_UART_REG_SETF(uart, IER_DLH, PTIME_DLH7, pthre);
}
 
__STATIC_INLINE HW_UART_INT hw_uart_get_interrupt_id(HW_UART_ID uart)
{
        return (HW_UART_INT) (UBA(uart)->UART2_IIR_FCR_REG & 0xF);
}
 
__STATIC_INLINE void hw_uart_write_scr(const HW_UART_ID uart, uint8_t value)
{
        if (uart == HW_UART2) {
                REG_SETF(UART2, UART2_CONFIG_REG, ISO7816_SCRATCH_PAD, value);
        } else {
                UART->UART_SCR_REG = value;
        }
}
 
__STATIC_INLINE uint8_t hw_uart_read_scr(const HW_UART_ID uart)
{
        uint8_t ret_val = 0;
        if (uart == HW_UART2) {
                ret_val =  REG_GETF(UART2, UART2_CONFIG_REG, ISO7816_SCRATCH_PAD);
        } else {
                ret_val = UART->UART_SCR_REG;
        }
        return ret_val;
}
 
//==================== Configuration functions =================================
void hw_uart_set_sclk(const HW_UART_ID uart, bool sclk);
 
HW_UART_BAUDRATE hw_uart_baudrate_get(HW_UART_ID uart);
 
void hw_uart_baudrate_set(HW_UART_ID uart, HW_UART_BAUDRATE baud_rate);
 
//=========================== FIFO control functions ===========================
 
__STATIC_INLINE bool hw_uart_is_data_ready(HW_UART_ID uart)
{
        return (UBA(uart)->UART2_LSR_REG & 1) != 0;
}
 
__STATIC_INLINE bool hw_uart_is_fifo_enabled(HW_UART_ID uart)
{
 
        return UBA(uart)->UART2_SFE_REG != 0;
}
 
__STATIC_INLINE void hw_uart_disable_fifo(HW_UART_ID uart)
{
        uint16_t iir_fcr_reg = UBA(uart)->UART2_IIR_FCR_REG;
        iir_fcr_reg &= 0xfffe;
        UBA(uart)->UART2_IIR_FCR_REG = iir_fcr_reg;
}
 
__STATIC_INLINE void hw_uart_enable_fifo(HW_UART_ID uart)
{
 
        UBA(uart)->UART2_SFE_REG = 1 << HW_UART_REG_FIELD_POS(2, SFE, UART_SHADOW_FIFO_ENABLE);
}
 
__STATIC_INLINE bool hw_uart_receive_fifo_not_empty(HW_UART_ID uart)
{
 
        return HW_UART_REG_GETF(uart, USR, UART_RFNE) != 0;
}
 
__STATIC_INLINE bool hw_uart_transmit_fifo_not_full(HW_UART_ID uart)
{
 
        return HW_UART_REG_GETF(uart, USR, UART_TFNF) != 0;
}
 
__STATIC_INLINE bool hw_uart_transmit_fifo_empty(HW_UART_ID uart)
{
        return HW_UART_REG_GETF(uart, USR, UART_TFE) != 0;
}
 
__STATIC_INLINE uint16_t hw_uart_receive_fifo_count(HW_UART_ID uart)
{
 
        return UBA(uart)->UART2_RFL_REG;
}
 
__STATIC_INLINE uint16_t hw_uart_transmit_fifo_count(HW_UART_ID uart)
{
 
        return UBA(uart)->UART2_TFL_REG;
}
 
__STATIC_INLINE void hw_uart_enable_loopback(HW_UART_ID uart)
{
        HW_UART_REG_SETF(uart, MCR, UART_LB, 1);
}
 
__STATIC_INLINE void hw_uart_disable_loopback(HW_UART_ID uart)
{
        HW_UART_REG_SETF(uart, MCR, UART_LB, 0);
}
 
uint8_t hw_uart_fifo_en_getf(HW_UART_ID uart);
 
__STATIC_INLINE void hw_uart_fifo_en_setf(HW_UART_ID uart, uint8_t en)
{
 
        // Write FIFO Enable (FIFOE) bit in FIFO Control Register
        uint16_t iir_fcr_reg = UBA(uart)->UART2_IIR_FCR_REG;
        iir_fcr_reg &= ~0x1;
        iir_fcr_reg |= (en & 0x1);
        UBA(uart)->UART2_IIR_FCR_REG = iir_fcr_reg;
}
 
__STATIC_INLINE uint8_t hw_uart_rx_fifo_tr_lvl_getf(HW_UART_ID uart)
{
 
        return UBA(uart)->UART2_SRT_REG & UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk;
}
 
__STATIC_INLINE void hw_uart_rx_fifo_tr_lvl_setf(HW_UART_ID uart, uint8_t tr_lvl)
{
 
        UBA(uart)->UART2_SRT_REG = tr_lvl;
}
 
uint8_t hw_uart_tx_fifo_tr_lvl_getf(HW_UART_ID uart);
 
__STATIC_INLINE void hw_uart_tx_fifo_tr_lvl_setf(HW_UART_ID uart, uint8_t tr_lvl)
{
 
        UBA(uart)->UART2_STET_REG = tr_lvl;
}
 
__STATIC_INLINE void hw_uart_tx_fifo_flush(HW_UART_ID uart)
{
        HW_UART_REG_SETF(uart, SRR, UART_XFR, 1);
}
 
__STATIC_INLINE void hw_uart_rx_fifo_flush(HW_UART_ID uart)
{
        HW_UART_REG_SETF(uart, SRR, UART_RFR, 1);
        /* Read also RBR in order to make sure that the character timeout IRQ (if any) is cleared. */
        hw_uart_rxdata_getf(uart);
}
 
__STATIC_INLINE bool hw_uart_read_buf_empty(HW_UART_ID uart)
{
        return !HW_UART_REG_GETF(uart, LSR, UART_DR);
}
 
__STATIC_INLINE bool hw_uart_write_buf_full(HW_UART_ID uart)
{
        return !HW_UART_REG_GETF(uart, LSR, UART_THRE);
}
 
__STATIC_INLINE bool hw_uart_transmit_empty(HW_UART_ID uart)
{
        return HW_UART_REG_GETF(uart, LSR, UART_TEMT);
}
 
#if (dg_configUART_SOFTWARE_FIFO == 1)
 
void hw_uart_set_soft_fifo(HW_UART_ID uart, uint8_t *buf, uint8_t size);
#endif /* dg_configUART_SOFTWARE_FIFO */
 
#if (HW_UART_DMA_SUPPORT == 1)
//=========================== DMA control functions ============================
 
__STATIC_INLINE void hw_uart_dma_mode_setf(HW_UART_ID uart, uint8_t dma_mode)
{
 
        UBA(uart)->UART2_SDMAM_REG = ((dma_mode & 1) << UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos)
                                        << UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk;
}
 
__STATIC_INLINE void hw_uart_clear_dma_request(HW_UART_ID uart)
{
        UBA(uart)->UART2_DMASA_REG = 1;
}
#endif /* HW_UART_DMA_SUPPORT */
//=========================== Line control functions ============================
 
HW_UART_CONFIG_ERR hw_uart_init(HW_UART_ID uart, const uart_config *cfg);
 
void hw_uart_deinit(HW_UART_ID uart);
 
void hw_uart_reinit(HW_UART_ID uart, const uart_config *cfg);
 
void hw_uart_cfg_get(HW_UART_ID uart, uart_config *cfg);
 
//=========================== Modem control functions ==========================
uint8_t hw_uart_afce_getf(HW_UART_ID uart);
 
void hw_uart_afce_setf(HW_UART_ID uart, uint8_t afce);
 
uint8_t hw_uart_loopback_getf(HW_UART_ID uart);
 
void hw_uart_loopback_setf(HW_UART_ID uart, uint8_t lb);
 
uint8_t hw_uart_rts_getf(HW_UART_ID uart);
 
void hw_uart_rts_setf(HW_UART_ID uart, uint8_t rtsn);
 
//=========================== Line status functions ============================
 
HW_UART_ERROR hw_uart_error_getf(HW_UART_ID uart);
 
uint8_t hw_uart_rx_fifo_err_getf(HW_UART_ID uart);
 
uint8_t hw_uart_is_tx_fifo_empty(HW_UART_ID uart);
 
uint8_t hw_uart_thr_empty_getf(HW_UART_ID uart);
 
uint8_t hw_uart_break_int_getf(HW_UART_ID uart);
 
uint8_t hw_uart_frame_err_getf(HW_UART_ID uart);
 
uint8_t hw_uart_parity_err_getf(HW_UART_ID uart);
 
uint8_t hw_uart_overrun_err_getf(HW_UART_ID uart);
 
//=========================== Modem status functions ===========================
 
uint8_t hw_uart_cts_getf(HW_UART_ID uart);
 
uint8_t hw_uart_delta_cts_getf(HW_UART_ID uart);
 
bool hw_uart_tx_in_progress(const HW_UART_ID uart);
 
bool hw_uart_rx_in_progress(const HW_UART_ID uart);
 
#if (dg_configUART_RX_CIRCULAR_DMA == 1)
 
void hw_uart_enable_rx_circular_dma(HW_UART_ID uart);
 
void hw_uart_copy_rx_circular_dma_buffer(HW_UART_ID uart, uint8_t *buf, uint16_t len);
 
#endif /* dg_configUART_RX_CIRCULAR_DMA */
 
#endif /* dg_configUSE_HW_UART */
 
 
#endif /* HW_UART_H_ */