hw_i2c.h

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#ifndef HW_I2C_H_
#define HW_I2C_H_
 
 
#if dg_configUSE_HW_I2C
 
#include <stdbool.h>
#include <stdint.h>
#include "sdk_defs.h"
 
#define HW_I2C_DMA_SUPPORT              dg_configI2C_DMA_SUPPORT
 
#if HW_I2C_DMA_SUPPORT
#include "hw_dma.h"
#endif
 
#ifndef HW_I2C_SLAVE_SUPPORT
#define HW_I2C_SLAVE_SUPPORT            ( 1 )
#endif
 
/* I2C Base Address */
#define IBA(id)                       ((I2C_Type *)id)
 
#define I2C_FIFO_DEPTH   (4)
 
#define I2C_SETUP(id, seq)           \
        do {                         \
                hw_i2c_disable(id);  \
                seq;                 \
                hw_i2c_enable(id);   \
        } while (0);
 
#define HW_I2C1         ((void *)I2C_BASE)
#if defined(I2C2)
#define HW_I2C2         ((void *)I2C2_BASE)
#endif
#if defined(I2C3)
#define HW_I2C3         ((void *)I2C3_BASE)
#endif
typedef void * HW_I2C_ID;
 
/*
 * Flags passed to read/write operations
 */
#define HW_I2C_F_NONE                   0x00000000      
#define HW_I2C_F_WAIT_FOR_STOP          0x00000001      
#define HW_I2C_F_ADD_STOP               0x00000002      
#define HW_I2C_F_ADD_RESTART            0x00000004      
#define HW_I2C_I2C1_MADDR       0x01
#if defined(HW_I2C2)
#define HW_I2C_I2C2_MADDR       0x05
#endif
#if defined(HW_I2C3)
#define HW_I2C_I2C3_MADDR       0x07
#endif
 
typedef enum {
   HW_I2C_ABORT_NONE = 0,                                                                 
   HW_I2C_ABORT_7B_ADDR_NO_ACK = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk,       
   HW_I2C_ABORT_10B_ADDR1_NO_ACK = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk,     
   HW_I2C_ABORT_10B_ADDR2_NO_ACK = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk,     
   HW_I2C_ABORT_TX_DATA_NO_ACK = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk,        
   HW_I2C_ABORT_GENERAL_CALL_NO_ACK = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk,    
   HW_I2C_ABORT_GENERAL_CALL_READ = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk,       
   HW_I2C_ABORT_START_BYTE_ACK = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk,        
   HW_I2C_ABORT_10B_READ_NO_RESTART = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk, 
   HW_I2C_ABORT_MASTER_DISABLED = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk,         
   HW_I2C_ABORT_ARBITRATION_LOST = I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk,               
   HW_I2C_ABORT_SLAVE_FLUSH_TX_FIFO = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk,
   HW_I2C_ABORT_SLAVE_ARBITRATION_LOST = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk, 
   HW_I2C_ABORT_SLAVE_IN_TX = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk,             
   HW_I2C_ABORT_USER_ABORT = I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk,               
   HW_I2C_ABORT_SW_ERROR                                                                  
} HW_I2C_ABORT_SOURCE;
 
typedef enum {
        HW_I2C_SPEED_STANDARD = 0,  
        HW_I2C_SPEED_FAST,          
        HW_I2C_SPEED_HIGH           
} HW_I2C_SPEED;
 
typedef enum {
        HW_I2C_MODE_MASTER = 0,  
        HW_I2C_MODE_SLAVE        
} HW_I2C_MODE;
 
typedef enum {
        HW_I2C_ADDRESSING_7B = 0,  
        HW_I2C_ADDRESSING_10B      
} HW_I2C_ADDRESSING;
 
#if (HW_I2C_SLAVE_SUPPORT == 1)
 
typedef enum {
        HW_I2C_EVENT_READ_REQUEST = 0,  
        HW_I2C_EVENT_DATA_READY,        
        HW_I2C_EVENT_TX_ABORT,          
        HW_I2C_EVENT_RX_OVERFLOW,       
        HW_I2C_EVENT_INVALID            
} HW_I2C_EVENT;
#endif /* HW_I2C_SLAVE_SUPPORT */
 
typedef enum {
        HW_I2C_INT_RX_UNDERFLOW = I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk,     
        HW_I2C_INT_RX_OVERFLOW = I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk,       
        HW_I2C_INT_RX_FULL = I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk,           
        HW_I2C_INT_TX_OVERFLOW = I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk,       
        HW_I2C_INT_TX_EMPTY = I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk,         
        HW_I2C_INT_READ_REQUEST = I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk,       
        HW_I2C_INT_TX_ABORT = I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk,          
        HW_I2C_INT_RX_DONE = I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk,           
        HW_I2C_INT_ACTIVITY = I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk,         
        HW_I2C_INT_STOP_DETECTED = I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk,    
        HW_I2C_INT_START_DETECTED = I2C_I2C_INTR_STAT_REG_R_START_DET_Msk,  
        HW_I2C_INT_GENERAL_CALL = I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk      
} HW_I2C_INT;
 
#if (HW_I2C_DMA_SUPPORT == 1)
 
typedef enum {
        HW_I2C_DMA_TRANSFER_WRITE,
        HW_I2C_DMA_TRANSFER_MASTER_READ,
#if (HW_I2C_SLAVE_SUPPORT == 1)
        HW_I2C_DMA_TRANSFER_SLAVE_READ,
#endif
} HW_I2C_DMA_TRANSFER;
 
typedef hw_dma_periph_prio_t hw_i2c_dma_prio_t;
#endif /* HW_I2C_DMA_SUPPORT */
 
typedef void (*hw_i2c_interrupt_cb)(HW_I2C_ID id, uint16_t mask);
 
typedef void (*hw_i2c_complete_cb)(HW_I2C_ID id, void *cb_data, uint16_t len, bool success);
 
#if (HW_I2C_SLAVE_SUPPORT == 1)
 
typedef void (*hw_i2c_event_cb)(HW_I2C_ID id, HW_I2C_EVENT event);
#endif /* HW_I2C_SLAVE_SUPPORT */
 
typedef struct {
        struct {
                uint16_t ss_hcnt;       
                uint16_t ss_lcnt;       
                uint16_t fs_hcnt;       
                uint16_t fs_lcnt;       
                uint16_t hs_hcnt;       
                uint16_t hs_lcnt;       
                } clock_cfg;
 
        HW_I2C_SPEED        speed;      
        HW_I2C_MODE         mode;       
        HW_I2C_ADDRESSING   addr_mode;  
        uint16_t            address;    
#if (HW_I2C_SLAVE_SUPPORT == 1)
        hw_i2c_event_cb     event_cb;   
#endif /* HW_I2C_SLAVE_SUPPORT */
#if (HW_I2C_DMA_SUPPORT == 1)
        hw_i2c_dma_prio_t   dma_prio;   
#endif /* HW_I2C_DMA_SUPPORT */
} i2c_config;
 
#define HW_I2C_REG_SETF(id, reg, field, val) \
        IBA(id)->reg##_REG = ((IBA(id)->reg##_REG & ~(I2C_##reg##_REG_##field##_Msk)) | \
        ((I2C_##reg##_REG_##field##_Msk) & ((val) << (I2C_##reg##_REG_##field##_Pos))))
 
#define HW_I2C_REG_GETF(id, reg, field) \
        ((IBA(id)->reg##_REG & (I2C_##reg##_REG_##field##_Msk)) >> (I2C_##reg##_REG_##field##_Pos))
 
#define HW_I2C_REG_SET_FIELD(reg, field, var, val) \
        REG_SET_FIELD(I2C, reg##_REG, field, var, val)
 
void hw_i2c_enable_clk(const HW_I2C_ID id);
 
void hw_i2c_disable_clk(const HW_I2C_ID id);
 
bool hw_i2c_is_clk_enabled(const HW_I2C_ID id);
 
void hw_i2c_init(HW_I2C_ID id, const i2c_config *cfg);
 
void hw_i2c_deinit(HW_I2C_ID id);
 
void hw_i2c_configure(HW_I2C_ID id, const i2c_config *cfg);
 
__STATIC_INLINE void hw_i2c_enable(HW_I2C_ID id)
{
        HW_I2C_REG_SETF(id, I2C_ENABLE, I2C_EN, 1);
}
 
void hw_i2c_disable(HW_I2C_ID id);
 
__STATIC_INLINE bool hw_i2c_is_enabled(HW_I2C_ID id)
{
        return (!!(HW_I2C_REG_GETF(id, I2C_ENABLE_STATUS, IC_EN)));
}
 
__STATIC_INLINE uint16_t hw_i2c_get_enable_status(HW_I2C_ID id)
{
        return IBA(id)->I2C_ENABLE_STATUS_REG;
}
 
#if (HW_I2C_DMA_SUPPORT == 1)
 
void hw_i2c_reset_dma_cb(HW_I2C_ID id);
#endif
 
bool hw_i2c_is_occupied(HW_I2C_ID id);
 
void hw_i2c_register_int(HW_I2C_ID id, hw_i2c_interrupt_cb cb, uint16_t mask);
 
void hw_i2c_unregister_int(HW_I2C_ID id);
 
void hw_i2c_set_int_mask(HW_I2C_ID id, uint16_t mask);
 
uint16_t hw_i2c_get_int_mask(HW_I2C_ID id);
 
__STATIC_INLINE void hw_i2c_set_mode(HW_I2C_ID id, HW_I2C_MODE mode)
{
        // default to master mode, if incorrect value specified
        bool set_master = (mode != HW_I2C_MODE_SLAVE) ? 1 : 0;
#if (HW_I2C_SLAVE_SUPPORT == 0)
        ASSERT_WARNING(set_master);
#endif
        uint32_t tmp = IBA(id)->I2C_CON_REG;
        HW_I2C_REG_SET_FIELD(I2C_CON, I2C_MASTER_MODE, tmp, set_master ? 1 : 0);
        HW_I2C_REG_SET_FIELD(I2C_CON, I2C_SLAVE_DISABLE, tmp, set_master ? 1 : 0);
        IBA(id)->I2C_CON_REG = tmp;
}
 
 
__STATIC_INLINE uint8_t hw_i2c_is_master(HW_I2C_ID id)
{
        return HW_I2C_REG_GETF(id, I2C_CON, I2C_MASTER_MODE);
}
 
__STATIC_INLINE void hw_i2c_set_speed(HW_I2C_ID id, HW_I2C_SPEED speed)
{
        // default to standard mode (100kbit/s), if incorrect value specified
        switch (speed) {
        case HW_I2C_SPEED_HIGH:
                HW_I2C_REG_SETF(id, I2C_CON, I2C_SPEED, 3);
                break;
        case HW_I2C_SPEED_FAST:
                HW_I2C_REG_SETF(id, I2C_CON, I2C_SPEED, 2);
                break;
        case HW_I2C_SPEED_STANDARD:
        default:
                HW_I2C_REG_SETF(id, I2C_CON, I2C_SPEED, 1);
                break;
        }
}
 
__STATIC_INLINE void hw_i2c_set_restart_enabled(HW_I2C_ID id, bool enabled)
{
        HW_I2C_REG_SETF(id, I2C_CON, I2C_RESTART_EN, !!enabled);
}
 
__STATIC_INLINE void hw_i2c_set_general_call_enabled(HW_I2C_ID id, bool enabled)
{
        uint32_t tmp = IBA(id)->I2C_TAR_REG;
        HW_I2C_REG_SET_FIELD(I2C_TAR, SPECIAL, tmp, !!enabled);
        HW_I2C_REG_SET_FIELD(I2C_TAR, GC_OR_START, tmp, !enabled);
        IBA(id)->I2C_TAR_REG = tmp;
}
 
__STATIC_INLINE void hw_i2c_set_target_addressing_mode(HW_I2C_ID id, HW_I2C_ADDRESSING addr_mode)
{
        // default to 7b addressing, if incorrect value specified
        HW_I2C_REG_SETF(id, I2C_CON, I2C_10BITADDR_MASTER, (addr_mode == HW_I2C_ADDRESSING_10B) ? 1 : 0);
}
 
#if (HW_I2C_SLAVE_SUPPORT == 1)
 
__STATIC_INLINE void hw_i2c_set_slave_addressing_mode(HW_I2C_ID id, HW_I2C_ADDRESSING addr_mode)
{
        // default to 7b addressing, if incorrect value specified
        HW_I2C_REG_SETF(id, I2C_CON, I2C_10BITADDR_SLAVE, (addr_mode == HW_I2C_ADDRESSING_10B) ? 1 : 0);
}
 
__STATIC_INLINE void hw_i2c_set_slave_address(HW_I2C_ID id, uint16_t address)
{
        HW_I2C_REG_SETF(id, I2C_SAR, IC_SAR, address);
}
 
__STATIC_INLINE void hw_i2c_set_general_call_ack_enabled(HW_I2C_ID id, bool ack)
{
        HW_I2C_REG_SETF(id, I2C_ACK_GENERAL_CALL, ACK_GEN_CALL, !!ack);
}
#endif /* HW_I2C_SLAVE_SUPPORT */
 
void hw_i2c_setup_master(HW_I2C_ID id, HW_I2C_ADDRESSING addr_mode, uint16_t address);
 
#if (HW_I2C_SLAVE_SUPPORT == 1)
 
void hw_i2c_set_slave_callback(HW_I2C_ID id, hw_i2c_event_cb cb);
 
#if (HW_I2C_DMA_SUPPORT == 1)
 
void hw_i2c_register_slave_dma_read_callback(HW_I2C_ID id);
#endif /* HW_I2C_DMA_SUPPORT */
 
void hw_i2c_setup_slave(HW_I2C_ID id, HW_I2C_ADDRESSING addr_mode,
                        uint16_t address, hw_i2c_event_cb cb);
#endif /* HW_I2C_SLAVE_SUPPORT */
 
__STATIC_INLINE bool hw_i2c_is_master_busy(HW_I2C_ID id)
{
        return (!!(HW_I2C_REG_GETF(id, I2C_STATUS, MST_ACTIVITY)));
}
 
#if (HW_I2C_SLAVE_SUPPORT == 1)
 
__STATIC_INLINE bool hw_i2c_is_slave_busy(HW_I2C_ID id)
{
        return (!!(HW_I2C_REG_GETF(id, I2C_STATUS, SLV_ACTIVITY)));
}
#endif /* HW_I2C_SLAVE_SUPPORT */
 
__STATIC_INLINE bool hw_i2c_controler_is_busy(HW_I2C_ID id)
{
        return (!!(HW_I2C_REG_GETF(id, I2C_STATUS, I2C_ACTIVITY)));
}
 
__STATIC_INLINE bool hw_i2c_is_tx_fifo_empty(HW_I2C_ID id)
{
        return (!!(HW_I2C_REG_GETF(id, I2C_STATUS, TFE)));
}
 
__STATIC_INLINE bool hw_i2c_is_tx_fifo_not_full(HW_I2C_ID id)
{
        return (!!(HW_I2C_REG_GETF(id, I2C_STATUS, TFNF)));
}
 
__STATIC_INLINE bool hw_i2c_is_rx_fifo_full(HW_I2C_ID id)
{
        return (!!(HW_I2C_REG_GETF(id, I2C_STATUS, RFF)));
}
 
__STATIC_INLINE bool hw_i2c_is_rx_fifo_not_empty(HW_I2C_ID id)
{
        return (!!(HW_I2C_REG_GETF(id, I2C_STATUS, RFNE)));
}
 
__STATIC_INLINE void hw_i2c_set_target_address(HW_I2C_ID id, uint16_t address)
{
        if (hw_i2c_is_enabled(id)) {
                /* Wait for the master to become IDLE */
                while (hw_i2c_is_master_busy(id));
 
                /* Now is safe to disable the I2C to change the Target Address */
                hw_i2c_disable(id);
 
                /* Change the Target Address */
                HW_I2C_REG_SETF(id, I2C_TAR, IC_TAR, address);
 
                /* Enable again the I2C to use the new address */
                hw_i2c_enable(id);
 
        } else {
                /* Change the Target Address */
                HW_I2C_REG_SETF(id, I2C_TAR, IC_TAR, address);
        }
}
 
__STATIC_INLINE void hw_i2c_write_byte(HW_I2C_ID id, uint8_t byte)
{
        IBA(id)->I2C_DATA_CMD_REG = byte & (I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk | I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk);
}
 
size_t hw_i2c_write_buffer_sync(HW_I2C_ID id, const uint8_t *data, uint16_t len,
                                HW_I2C_ABORT_SOURCE *abrt_code, uint32_t flags);
 
int hw_i2c_write_buffer_async(HW_I2C_ID id, const uint8_t *data, uint16_t len,
                              hw_i2c_complete_cb cb, void *cb_data, uint32_t flags);
 
__STATIC_INLINE void hw_i2c_read_byte_trigger(HW_I2C_ID id)
{
        IBA(id)->I2C_DATA_CMD_REG = I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk;
}
 
size_t hw_i2c_read_buffer_sync(HW_I2C_ID id, uint8_t *data, uint16_t len,
                               HW_I2C_ABORT_SOURCE *abrt_code, uint32_t flags);
 
int hw_i2c_read_buffer_async(HW_I2C_ID id, uint8_t *data, uint16_t len,
                             hw_i2c_complete_cb cb, void *cb_data, uint32_t flags);
 
int hw_i2c_write_then_read_async(HW_I2C_ID id, const uint8_t *w_data, uint16_t w_len,
                                        uint8_t *r_data, uint16_t r_len, hw_i2c_complete_cb cb,
                                        void *cb_data, uint32_t flags);
 
__STATIC_INLINE uint8_t hw_i2c_read_byte(HW_I2C_ID id)
{
        return HW_I2C_REG_GETF(id, I2C_DATA_CMD, I2C_DAT);
}
 
__STATIC_INLINE void hw_i2c_set_tx_fifo_threshold(HW_I2C_ID id, uint8_t level)
{
        HW_I2C_REG_SETF(id, I2C_TX_TL, TX_TL, level);
}
 
__STATIC_INLINE void hw_i2c_set_rx_fifo_threshold(HW_I2C_ID id, uint8_t level)
{
        HW_I2C_REG_SETF(id, I2C_RX_TL, RX_TL, level);
}
 
__STATIC_INLINE uint8_t hw_i2c_get_tx_fifo_threshold(HW_I2C_ID id)
{
        return HW_I2C_REG_GETF(id, I2C_TX_TL, TX_TL);
}
 
__STATIC_INLINE uint8_t hw_i2c_get_rx_fifo_threshold(HW_I2C_ID id)
{
        return HW_I2C_REG_GETF(id, I2C_RX_TL, RX_TL);
}
 
__STATIC_INLINE uint8_t hw_i2c_get_tx_fifo_level(HW_I2C_ID id)
{
        return HW_I2C_REG_GETF(id, I2C_TXFLR, TXFLR);
}
 
__STATIC_INLINE uint8_t hw_i2c_get_rx_fifo_level(HW_I2C_ID id)
{
        return HW_I2C_REG_GETF(id, I2C_RXFLR, RXFLR);
}
 
__STATIC_INLINE void hw_i2c_flush_rx_fifo(HW_I2C_ID id)
{
        while (hw_i2c_get_rx_fifo_level(id)) {
                hw_i2c_read_byte(id);
        }
}
 
__STATIC_INLINE uint16_t hw_i2c_get_int_state(HW_I2C_ID id)
{
        return IBA(id)->I2C_INTR_STAT_REG;
}
 
__STATIC_INLINE uint16_t hw_i2c_get_raw_int_state(HW_I2C_ID id)
{
        return IBA(id)->I2C_RAW_INTR_STAT_REG;
}
 
__STATIC_INLINE void hw_i2c_reset_int_all(HW_I2C_ID id)
{
        (void) IBA(id)->I2C_CLR_INTR_REG;
}
 
__STATIC_INLINE void hw_i2c_reset_int_rx_underflow(HW_I2C_ID id)
{
        (void) IBA(id)->I2C_CLR_RX_UNDER_REG;
}
 
__STATIC_INLINE void hw_i2c_reset_int_rx_overflow(HW_I2C_ID id)
{
        (void) IBA(id)->I2C_CLR_RX_OVER_REG;
}
 
__STATIC_INLINE void hw_i2c_reset_int_tx_overflow(HW_I2C_ID id)
{
        (void) IBA(id)->I2C_CLR_TX_OVER_REG;
}
 
__STATIC_INLINE void hw_i2c_reset_int_read_request(HW_I2C_ID id)
{
        (void) IBA(id)->I2C_CLR_RD_REQ_REG;
}
 
__STATIC_INLINE void hw_i2c_reset_int_tx_abort(HW_I2C_ID id)
{
        (void) IBA(id)->I2C_CLR_TX_ABRT_REG;
}
 
__STATIC_INLINE void hw_i2c_reset_int_rx_done(HW_I2C_ID id)
{
        (void) IBA(id)->I2C_CLR_RX_DONE_REG;
}
 
__STATIC_INLINE void hw_i2c_reset_int_activity(HW_I2C_ID id)
{
        (void) IBA(id)->I2C_CLR_ACTIVITY_REG;
}
 
__STATIC_INLINE void hw_i2c_reset_int_start_detected(HW_I2C_ID id)
{
        (void) IBA(id)->I2C_CLR_START_DET_REG;
}
 
__STATIC_INLINE void hw_i2c_reset_int_stop_detected(HW_I2C_ID id)
{
        (void) IBA(id)->I2C_CLR_STOP_DET_REG;
}
 
__STATIC_INLINE void hw_i2c_reset_int_gen_call(HW_I2C_ID id)
{
        (void) IBA(id)->I2C_CLR_GEN_CALL_REG;
}
 
__STATIC_INLINE uint32_t hw_i2c_get_abort_source(HW_I2C_ID id)
{
        return IBA(id)->I2C_TX_ABRT_SOURCE_REG & 0x1FFFF;
}
 
__STATIC_INLINE void hw_i2c_reset_abort_source(HW_I2C_ID id)
{
        hw_i2c_reset_int_tx_abort(id);
}
 
__STATIC_INLINE void hw_i2c_master_abort_transfer(HW_I2C_ID id)
{
        if (hw_i2c_is_master(id)) {
                HW_I2C_REG_SETF(id, I2C_ENABLE, I2C_ABORT, 1);
        }
}
 
 
#if (HW_I2C_DMA_SUPPORT == 1)
 
void hw_i2c_prepare_dma(HW_I2C_ID id, uint8_t channel, void *data, uint16_t len,
                HW_I2C_DMA_TRANSFER type, hw_i2c_complete_cb cb, void *cb_data,
                uint32_t flags);
 
 
void hw_i2c_dma_start(HW_I2C_ID id);
 
void hw_i2c_write_buffer_dma(HW_I2C_ID id, uint8_t channel, const uint16_t *data, uint16_t len,
                                          hw_i2c_complete_cb cb, void *cb_data, uint32_t flags);
 
 
void hw_i2c_read_buffer_dma(HW_I2C_ID id, uint8_t channel, uint8_t *data, uint16_t len,
                                   hw_i2c_complete_cb cb, void *cb_data, uint32_t flags);
 
 
#endif /* HW_I2C_DMA_SUPPORT */
 
#endif /* dg_configUSE_HW_I2C */
#endif /* HW_I2C_H_ */