hw_clk_da1459x.h

Go to the documentation of this file.

 
#ifndef HW_CLK_DA1459x_H_
#define HW_CLK_DA1459x_H_
 
 
#if dg_configUSE_HW_CLK
 
#include "sdk_defs.h"
#include "hw_sys.h"
#if (dg_configHW_FCU_WAIT_CYCLES_MODE)
#include "../src/hw_sys_internal.h"
#endif
 
#define HW_CLK_DELAY_OVERHEAD_CYCLES   (72)
#define HW_CLK_CYCLES_PER_DELAY_REP    (4)
 
#define XTAL32M_USEC_TO_250K_CYCLES(x)  ((uint16_t)((x * (dg_configRC32M_FREQ/1000000) + 127) / 128))
 
#define XTALRDY_CYCLES_TO_LP_CLK_CYCLES(x, lp_freq) ((((uint32_t)(x)) * lp_freq + dg_configRC32M_FREQ_MIN/(128) - 1) / (dg_configRC32M_FREQ_MIN/128))
 
typedef enum sys_clk_is_type {
        SYS_CLK_IS_XTAL32M = 0,
        SYS_CLK_IS_RC32,
        SYS_CLK_IS_LP,
        SYS_CLK_IS_DBLR,
        SYS_CLK_IS_INVALID
} sys_clk_is_t;
 
typedef enum cal_clk_sel_type {
        CALIBRATE_RCLP = 0,
        CALIBRATE_RC32M,
        CALIBRATE_XTAL32K,
        CALIBRATE_RCX,
        CALIBRATE_RCOSC,
} cal_clk_t;
 
typedef enum cal_ref_clk_sel_type {
        CALIBRATE_REF_DIVN = 0,
        CALIBRATE_REF_RCLP,
        CALIBRATE_REF_RC32M,
        CALIBRATE_REF_XTAL32K,
        CALIBRATE_REF_RCOSC,
        CALIBRATE_REF_EXT,
} cal_ref_clk_t;
 
typedef enum sysclk_type {
        sysclk_RC32    = 0,     
        sysclk_XTAL32M = 2,     
        sysclk_DBLR64  = 4,     
        sysclk_LP      = 255,   
} sys_clk_t;
 
typedef enum rclp_mode_type {
        RCLP_DEFAULT    = 0,                                                            
        RCLP_FORCE_SLOW = REG_MSK(CRG_TOP, CLK_RCLP_REG, RCLP_LOW_SPEED_FORCE),         
        RCLP_FORCE_FAST = REG_MSK(CRG_TOP, CLK_RCLP_REG, RCLP_HIGH_SPEED_FORCE),        
} rclp_mode_t;
 
typedef enum cpu_clk_type {
        cpuclk_2M = 2,          
        cpuclk_4M = 4,          
        cpuclk_8M = 8,          
        cpuclk_16M = 16,        
        cpuclk_32M = 32,        
        cpuclk_64M = 64         
} cpu_clk_t;
 
__STATIC_INLINE bool hw_clk_check_rc32_status(void)
{
        return REG_GETF(CRG_TOP, CLK_RC32M_REG, RC32M_ENABLE);
}
 
__STATIC_INLINE void hw_clk_enable_rc32(void)
{
        REG_SET_BIT(CRG_TOP, CLK_RC32M_REG, RC32M_ENABLE);
}
 
__STATIC_FORCEINLINE void hw_clk_disable_rc32(void)
{
        REG_CLR_BIT(CRG_TOP, CLK_RC32M_REG, RC32M_ENABLE);
}
 
void hw_clk_set_xtalm_settling_time(uint8_t cycles, bool high_clock);
 
__STATIC_FORCEINLINE uint16_t hw_clk_get_xtalm_settling_time(void)
{
        uint32_t val = CRG_XTAL->XTAL32M_IRQ_CTRL_REG;
        uint16_t cycles = REG_GET_FIELD(CRG_XTAL, XTAL32M_IRQ_CTRL_REG, XTAL32M_IRQ_CNT, val);
 
        if (REG_GET_FIELD(CRG_XTAL, XTAL32M_IRQ_CTRL_REG, XTAL32M_IRQ_CLK, val) == 1) {
                // 31.25kHz clock cycles. Convert them to 250kHz clock cycles.
                cycles *= 8;
        }
        return cycles;
}
 
__STATIC_INLINE bool hw_clk_check_xtalm_status(void)
{
        return REG_GETF(CRG_XTAL, XTAL32M_STAT0_REG, XTAL32M_READY) == 1;
}
 
__STATIC_INLINE void hw_clk_enable_xtalm(void)
{
        /* Do nothing if XTAL32M is already up and running. */
        if (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_XTAL32M)) {
                return;
        }
 
        // Check if TIM power domain is enabled
        ASSERT_WARNING(REG_GETF(CRG_TOP, SYS_STAT_REG, TIM_IS_UP));
 
        // Check the power supply
 
        /* Enable the XTAL oscillator. */
        REG_SET_BIT(CRG_XTAL, XTAL32M_CTRL_REG, XTAL32M_ENABLE);
}
 
__STATIC_INLINE void hw_clk_disable_xtalm(void)
{
        REG_CLR_BIT(CRG_XTAL, XTAL32M_CTRL_REG, XTAL32M_ENABLE);
}
 
__STATIC_INLINE bool hw_clk_is_xtalm_started(void)
{
        return (REG_GETF(CRG_XTAL, XTAL32M_STAT0_REG, XTAL32M_READY) &&
                REG_GETF(CRG_XTAL, XTAL32M_IRQ_STAT_REG, XTAL32M_IRQ_COUNT_STAT) == 0);
}
 
__STATIC_FORCEINLINE sys_clk_is_t hw_clk_get_sysclk(void)
{
        static const uint32_t freq_msk = CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Msk |
                                   CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk |
                                   CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk |
                                   CRG_TOP_CLK_CTRL_REG_RUNNING_AT_DBLR64M_Msk;
 
        static __RETAINED_CONST_INIT const sys_clk_is_t clocks[] = {
                SYS_CLK_IS_LP,          // 0b000
                SYS_CLK_IS_RC32,        // 0b001
                SYS_CLK_IS_XTAL32M,     // 0b010
                SYS_CLK_IS_INVALID,
                SYS_CLK_IS_DBLR         // 0b100
        };
 
        // drop bit0 to reduce the size of clocks[]
        uint32_t index = (CRG_TOP->CLK_CTRL_REG & freq_msk) >> (CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Pos + 1);
        ASSERT_WARNING(index <= 4);
 
        sys_clk_is_t clk = clocks[index];
        ASSERT_WARNING(clk != SYS_CLK_IS_INVALID);
        return clk;
}
 
__RETAINED_CODE sys_clk_t hw_clk_get_system_clock(void);
 
__STATIC_INLINE bool hw_clk_lp_is_xtal32k(void)
{
        return REG_GETF(CRG_TOP, CLK_XTAL32K_REG, XTAL32K_ENABLE) &&
              (REG_GETF(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL) == LP_CLK_IS_XTAL32K);
}
 
__STATIC_INLINE bool hw_clk_lp_is_rclp(void)
{
        return (!REG_GETF(CRG_TOP, CLK_RCLP_REG, RCLP_DISABLE)) &&
              (REG_GETF(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL) == LP_CLK_IS_RCLP);
}
 
__STATIC_INLINE bool hw_clk_lp_is_rcx(void)
{
        return REG_GETF(CRG_TOP, CLK_RCX_REG, RCX_ENABLE) &&
              (REG_GETF(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL) == LP_CLK_IS_RCX);
}
 
__STATIC_INLINE bool hw_clk_lp_is_external(void)
{
        return REG_GETF(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL) == LP_CLK_IS_EXTERNAL;
}
 
__STATIC_INLINE void hw_clk_lp_set_rcx(void)
{
        ASSERT_WARNING(__get_PRIMASK() == 1 || __get_BASEPRI());
        ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_RCX_REG, RCX_ENABLE));
 
        REG_SETF(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL, LP_CLK_IS_RCX);
}
 
__STATIC_INLINE void hw_clk_lp_set_xtal32k(void)
{
        ASSERT_WARNING(__get_PRIMASK() == 1 || __get_BASEPRI());
        ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_XTAL32K_REG, XTAL32K_ENABLE));
 
        REG_SETF(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL, LP_CLK_IS_XTAL32K);
}
 
__STATIC_INLINE void hw_clk_lp_set_ext32k(void)
{
        ASSERT_WARNING(__get_PRIMASK() == 1 || __get_BASEPRI());
 
        REG_SETF(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL, LP_CLK_IS_EXTERNAL);
}
 
__STATIC_INLINE void hw_clk_set_rclp_mode(rclp_mode_t mode)
{
        GLOBAL_INT_DISABLE();
        switch (mode) {
        case RCLP_DEFAULT:
                REG_SET_MASKED(CRG_TOP, CLK_RCLP_REG, (RCLP_FORCE_SLOW | RCLP_FORCE_FAST), RCLP_DEFAULT);
                break;
        case RCLP_FORCE_SLOW:
                REG_SET_MASKED(CRG_TOP, CLK_RCLP_REG, (RCLP_FORCE_SLOW | RCLP_FORCE_FAST), RCLP_FORCE_SLOW);
                break;
        case RCLP_FORCE_FAST:
                REG_SET_MASKED(CRG_TOP, CLK_RCLP_REG, (RCLP_FORCE_SLOW | RCLP_FORCE_FAST), RCLP_FORCE_FAST);
                break;
        default:
                ASSERT_WARNING(0);
                break;
        }
        GLOBAL_INT_RESTORE();
}
 
__STATIC_INLINE rclp_mode_t hw_clk_get_rclp_mode(void)
{
        return (CRG_TOP->CLK_RCLP_REG & (RCLP_FORCE_SLOW | RCLP_FORCE_FAST));
}
 
__STATIC_INLINE void hw_clk_enable_rclp(void)
{
        REG_CLR_BIT(CRG_TOP, CLK_RCLP_REG, RCLP_DISABLE);
}
 
__STATIC_INLINE void hw_clk_disable_rclp(void)
{
        ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL) != LP_CLK_IS_RCLP);
 
        REG_SET_BIT(CRG_TOP, CLK_RCLP_REG, RCLP_DISABLE);
}
 
__STATIC_INLINE void hw_clk_lp_set_rclp(void)
{
        ASSERT_WARNING(__get_PRIMASK() == 1 || __get_BASEPRI());
        ASSERT_WARNING(!REG_GETF(CRG_TOP, CLK_RCLP_REG, RCLP_DISABLE));
 
        REG_SETF(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL, LP_CLK_IS_RCLP);
}
 
__STATIC_INLINE void hw_clk_configure_rcx(void)
{
        // Reset values for CLK_RCX_REG register should be used
}
 
__STATIC_INLINE void hw_clk_enable_rcx(void)
{
        REG_SET_BIT(CRG_TOP, CLK_RCX_REG, RCX_ENABLE);
}
 
__STATIC_INLINE void hw_clk_disable_rcx(void)
{
        ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL) != LP_CLK_IS_RCX);
 
        REG_CLR_BIT(CRG_TOP, CLK_RCX_REG, RCX_ENABLE);
}
 
__STATIC_INLINE void hw_clk_configure_xtal32k(void)
{
        // Configure xtal.
        uint32_t reg = CRG_TOP->CLK_XTAL32K_REG;
        REG_SET_FIELD(CRG_TOP, CLK_XTAL32K_REG, XTAL32K_CUR, reg, 5);
        REG_SET_FIELD(CRG_TOP, CLK_XTAL32K_REG, XTAL32K_RBIAS, reg, 3);
 
        REG_SET_FIELD(CRG_TOP, CLK_XTAL32K_REG, XTAL32K_DISABLE_AMPREG, reg, dg_configEXT_LP_IS_DIGITAL);
 
        CRG_TOP->CLK_XTAL32K_REG = reg;
}
 
__STATIC_INLINE void hw_clk_enable_xtal32k(void)
{
        REG_SET_BIT(CRG_TOP, CLK_XTAL32K_REG, XTAL32K_ENABLE);
}
 
__STATIC_INLINE void hw_clk_disable_xtal32k(void)
{
        ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL) != LP_CLK_IS_XTAL32K);
        REG_CLR_BIT(CRG_TOP, CLK_XTAL32K_REG, XTAL32K_ENABLE);
}
 
__STATIC_INLINE void hw_clk_calibration_enable_irq(void)
{
        REG_SET_BIT(ANAMISC_BIF, CLK_CAL_IRQ_REG, CLK_CAL_IRQ_EN);
}
 
__STATIC_INLINE void hw_clk_calibration_clear_irq(void)
{
        REG_SET_BIT(ANAMISC_BIF, CLK_CAL_IRQ_REG, CLK_CAL_IRQ_CLR);
}
 
__STATIC_INLINE bool hw_clk_calibration_status_irq(void)
{
        return REG_GETF(ANAMISC_BIF, CLK_CAL_IRQ_REG, CLK_CAL_IRQ_STATUS) == 0;
}
 
__STATIC_INLINE bool hw_clk_calibration_finished(void)
{
        return REG_GETF(ANAMISC_BIF, CLK_REF_SEL_REG, REF_CAL_START) == 0;
}
 
void hw_clk_start_calibration(cal_clk_t clk_type, cal_ref_clk_t clk_ref_type, uint16_t cycles);
 
uint32_t hw_clk_get_calibration_data(void);
 
__STATIC_INLINE void hw_clk_set_sysclk(sys_clk_is_t mode)
{
        /* Make sure a valid sys clock is requested */
        ASSERT_WARNING(mode <= SYS_CLK_IS_DBLR);
 
        /* Switch to Doubler is only allowed when current system clock is XTAL32M */
        ASSERT_WARNING(mode != SYS_CLK_IS_DBLR ||
                REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_XTAL32M)  ||
                REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_DBLR64M))
 
        /* Switch to Doubler is only allowed when HDIV and PDIV are 0 */
        ASSERT_WARNING(mode != SYS_CLK_IS_DBLR || (hw_clk_get_hclk_div() == ahb_div1 &&  hw_clk_get_pclk_div() == apb_div1));
 
        /* Switch from Doubler is only allowed when new system clock is XTAL32M */
        ASSERT_WARNING(!REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_DBLR64M) ||
                mode == SYS_CLK_IS_XTAL32M  ||
                mode == SYS_CLK_IS_DBLR);
 
#if dg_configHW_FCU_WAIT_CYCLES_MODE
        hw_sys_fcu_set_max_wait_cycles();
#endif
        if (mode == SYS_CLK_IS_XTAL32M && REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_RC32M)) {
                REG_SET_BIT(CRG_TOP, CLK_SWITCH2XTAL_REG, SWITCH2XTAL);
        }
        else {
                GLOBAL_INT_DISABLE();
                REG_SETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL, mode);
                GLOBAL_INT_RESTORE();
        }
 
        /* Wait until the switch is done! */
        switch (mode) {
        case SYS_CLK_IS_XTAL32M:
                while (!REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_XTAL32M)) {
                }
                break;
 
        case SYS_CLK_IS_RC32:
                while (!REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_RC32M)) {
                }
                break;
 
        case SYS_CLK_IS_LP:
                while (!REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_LP_CLK)) {
                }
                break;
 
        case SYS_CLK_IS_DBLR:
                while (!REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_DBLR64M)) {
                }
                break;
        default:
                ASSERT_WARNING(0);
        }
#if dg_configHW_FCU_WAIT_CYCLES_MODE
        hw_sys_fcu_set_optimum_wait_cycles();
#endif
}
 
__STATIC_FORCEINLINE void hw_clk_set_hclk_div(ahb_div_t div)
{
        ASSERT_WARNING(div <= ahb_div16);
        GLOBAL_INT_DISABLE();
#if dg_configHW_FCU_WAIT_CYCLES_MODE
        hw_sys_fcu_set_max_wait_cycles();
        REG_SETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV, div);
        hw_sys_fcu_set_optimum_wait_cycles();
#else
        REG_SETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV, div);
#endif
        GLOBAL_INT_RESTORE();
}
 
__STATIC_FORCEINLINE void hw_clk_dblr_sys_on(void)
{
        GLOBAL_INT_DISABLE();
 
        /* XTAL32M_LDO_LEVEL voltage must be set to 0.9V prior to enabling DBLR */
        ASSERT_WARNING(REG_GETF(CRG_TOP, POWER_LEVEL_REG, XTAL32M_LDO_LEVEL) > 2);
 
        /* Release the reset of the Doubler Control Logic */
        REG_SET_BIT(CRG_XTAL, CLKDBLR_CTRL1_REG, RESET_N);
 
        /* Turn on DBLR. */
        REG_SET_BIT(CRG_XTAL, CLKDBLR_CTRL1_REG, ENABLE);
 
        GLOBAL_INT_RESTORE();
}
 
__STATIC_FORCEINLINE void hw_clk_dblr_sys_off(void)
{
        GLOBAL_INT_DISABLE();
 
        // The DBLR is not the system clk.
        ASSERT_WARNING(!REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_DBLR64M));
 
        /* Reset the Doubler Control Logic. */
        REG_CLR_BIT(CRG_XTAL, CLKDBLR_CTRL1_REG, RESET_N);
 
        /* Turn off DBLR. */
        REG_CLR_BIT(CRG_XTAL, CLKDBLR_CTRL1_REG, ENABLE);
 
        GLOBAL_INT_RESTORE();
}
 
__STATIC_INLINE bool hw_clk_check_dblr_status(void)
{
        return REG_GETF(CRG_XTAL, CLKDBLR_CTRL1_REG, ENABLE);
}
 
__STATIC_INLINE bool hw_clk_is_dblr_ready(void)
{
        return REG_GETF(CRG_XTAL, CLKDBLR_STATUS_REG , OUTPUT_READY);
}
 
__STATIC_INLINE void hw_clk_enable_sysclk(sys_clk_is_t clk)
{
        switch (clk) {
        case SYS_CLK_IS_XTAL32M:
                hw_clk_enable_xtalm();
                return;
        case SYS_CLK_IS_RC32:
                hw_clk_enable_rc32();
                return;
        case SYS_CLK_IS_DBLR:
                hw_clk_dblr_sys_on();
                return;
        default:
                /* An invalid clock is requested */
                ASSERT_WARNING(0);
        }
}
 
__STATIC_INLINE void hw_clk_disable_sysclk(sys_clk_is_t clk)
{
        switch (clk) {
        case SYS_CLK_IS_XTAL32M:
                hw_clk_disable_xtalm();
                return;
        case SYS_CLK_IS_RC32:
                hw_clk_disable_rc32();
                return;
        case SYS_CLK_IS_DBLR:
                hw_clk_dblr_sys_off();
                return;
        default:
                /* An invalid clock is requested */
                ASSERT_WARNING(0);
        }
}
 
__STATIC_INLINE bool hw_clk_is_enabled_sysclk(sys_clk_is_t clk)
{
        switch (clk) {
        case SYS_CLK_IS_XTAL32M:
                return hw_clk_check_xtalm_status();
        case SYS_CLK_IS_RC32:
                return hw_clk_check_rc32_status();
        case SYS_CLK_IS_DBLR:
                return hw_clk_check_dblr_status();
        default:
                /* An invalid clock is requested */
                ASSERT_WARNING(0);
                return false;
        }
}
 
__STATIC_FORCEINLINE void hw_clk_configure_ext32k_pins(void)
{
        GPIO-> P1_14_MODE_REG = 0;
}
 
int8_t hw_clk_xtalm_configure_cur_set(void);
 
void hw_clk_xtalm_configure_irq(void);
 
__STATIC_INLINE void hw_clk_xtalm_irq_enable(void)
{
        REG_SET_BIT(CRG_XTAL, XTAL32M_IRQ_CTRL_REG, XTAL32M_IRQ_ENABLE);
}
 
#endif /* dg_configUSE_HW_CLK */
 
 
#endif /* HW_CLK_DA1459x_H_ */