SmartSnippets DA1459x SDK
bsp_defaults_da1459x.h
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1 
40 #ifndef BSP_DEFAULTS_DA1459X_H_
41 #define BSP_DEFAULTS_DA1459X_H_
42 
43 
44 /* Deprecated configuration options must not be defined by the application. */
45 
46 #define DG_CONFIG_NA_59X_MSG DG_CONFIG_NOT_APPLICABLE_MSG " for the DA1459x device family."
47 #define DG_CONFIG_NA_59X_FORCE_ZERO_MSG DG_CONFIG_NA_59X_MSG " Forcing to 0 (not used)."
48 #define DG_CONFIG_TIMER_NA_MSG DG_CONFIG_NA_59X_MSG " Use the generic dg_configUSE_HW_TIMER instead."
49 
50 #ifdef dg_configTim1Prescaler
51 # pragma message "dg_configTim1Prescaler" DG_CONFIG_NA_59X_MSG
52 # undef dg_configTim1Prescaler
53 #endif
54 
55 #ifdef dg_configTim1PrescalerBitRange
56 # pragma message "dg_configTim1PrescalerBitRange" DG_CONFIG_NA_59X_MSG
57 # undef dg_configTim1PrescalerBitRange
58 #endif
59 
60 #ifdef dg_configEXT_CRYSTAL_FREQ
61 # pragma message "dg_configEXT_CRYSTAL_FREQ" DG_CONFIG_NA_59X_MSG
62 # undef dg_configEXT_CRYSTAL_FREQ
63 #endif
64 
65 #ifdef dg_configUSER_CAN_USE_TIMER1
66 # pragma message "dg_configUSER_CAN_USE_TIMER1" DG_CONFIG_NA_59X_MSG
67 # undef dg_configUSER_CAN_USE_TIMER1
68 #endif
69 
70 #if (dg_configUSE_HW_RF != 0)
71 # pragma message "dg_configUSE_HW_RF" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
72 # undef dg_configUSE_HW_RF
73 # define dg_configUSE_HW_RF 0
74 #endif
75 
76 #if (dg_configUSE_HW_COEX != 0)
77 # pragma message "dg_configUSE_HW_COEX" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
78 # undef dg_configUSE_HW_COEX
79 # define dg_configUSE_HW_COEX 0
80 #endif
81 
82 #if (dg_configUSE_HW_ERM != 0)
83 # pragma message "dg_configUSE_HW_ERM" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
84 # undef dg_configUSE_HW_ERM
85 # define dg_configUSE_HW_ERM 0
86 #endif
87 
88 #if (dg_configUSE_HW_LCDC != 0)
89 # pragma message "dg_configUSE_HW_LCDC" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
90 # undef dg_configUSE_HW_LCDC
91 # define dg_configUSE_HW_LCDC 0
92 #endif
93 
94 #if (dg_configUSE_HW_LRA != 0)
95 # pragma message "dg_configUSE_HW_LRA" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
96 # undef dg_configUSE_HW_LRA
97 # define dg_configUSE_HW_LRA 0
98 #endif
99 
100 #if (dg_configUSE_HW_OTPC != 0)
101 # pragma message "dg_configUSE_HW_OTPC" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
102 # undef dg_configUSE_HW_OTPC
103 # define dg_configUSE_HW_OTPC 0
104 #endif
105 
106 #if (dg_configUSE_IF_PDM != 0)
107 # pragma message "dg_configUSE_IF_PDM" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
108 # undef dg_configUSE_IF_PDM
109 # define dg_configUSE_IF_PDM 0
110 #endif
111 
112 #if (dg_configUSE_HW_IRGEN != 0)
113 # pragma message "dg_configUSE_HW_TEMPSENS" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
114 # undef dg_configUSE_HW_IRGEN
115 # define dg_configUSE_HW_IRGEN 0
116 #endif
117 
118 #if (dg_configUSE_HW_SOC != 0)
119 # pragma message "dg_configUSE_HW_SOC" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
120 # undef dg_configUSE_HW_SOC
121 # define dg_configUSE_HW_SOC 0
122 #endif
123 
124 #if (dg_configUSE_HW_TRNG != 0)
125 # pragma message "dg_configUSE_HW_TRNG" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
126 # undef dg_configUSE_HW_TRNG
127 # define dg_configUSE_HW_TRNG 0
128 #endif
129 
130 #if (dg_configUSE_HW_TIMER0 != 0)
131 # pragma message "dg_configUSE_HW_TIMERX" DG_CONFIG_TIMER_NA_MSG
132 # undef dg_configUSE_HW_TIMER0
133 # define dg_configUSE_HW_TIMER0 0
134 #endif
135 
136 #if (dg_configUSE_HW_TIMER1 != 0)
137 # pragma message "dg_configUSE_HW_TIMERX" DG_CONFIG_TIMER_NA_MSG
138 # undef dg_configUSE_HW_TIMER1
139 # define dg_configUSE_HW_TIMER1 0
140 #endif
141 
142 #if (dg_configUSE_HW_TIMER2 != 0)
143 # pragma message "dg_configUSE_HW_TIMERX" DG_CONFIG_TIMER_NA_MSG
144 # undef dg_configUSE_HW_TIMER2
145 # define dg_configUSE_HW_TIMER2 0
146 #endif
147 
148 #if (dg_configUSE_HW_USB != 0)
149 # pragma message "dg_configUSE_HW_USB" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
150 # undef dg_configUSE_HW_USB
151 # define dg_configUSE_HW_USB 0
152 #endif
153 
154 #if (dg_configUSE_HW_USB_CHARGER != 0)
155 # pragma message "dg_configUSE_HW_USB_CHARGER" DG_CONFIG_NA_59X_FORCE_ZERO_MSG
156 # undef dg_configUSE_HW_USB_CHARGER
157 # define dg_configUSE_HW_USB_CHARGER 0
158 #endif
159 
160 /* ------------------------------- Peripherals -------------------------------------------------- */
161 
209 /* -------------------------------- Peripherals (hw_*) selection -------------------------------- */
210 
211 #ifndef dg_configUSE_HW_AES
212 #define dg_configUSE_HW_AES (0)
213 #endif
214 
215 #ifndef dg_configUSE_HW_CACHE
216 #define dg_configUSE_HW_CACHE (1)
217 #endif
218 
219 #ifndef dg_configUSE_HW_CHARGER
220 #define dg_configUSE_HW_CHARGER (0)
221 #endif
222 
223 #ifndef dg_configUSE_HW_CLK
224 #define dg_configUSE_HW_CLK (1)
225 #endif
226 
227 #ifndef dg_configUSE_HW_CPM
228 #define dg_configUSE_HW_CPM (1)
229 #endif
230 
231 #ifndef dg_configUSE_HW_DMA
232 #define dg_configUSE_HW_DMA (1)
233 #endif
234 
235 #ifndef dg_configUSE_HW_GPADC
236 #define dg_configUSE_HW_GPADC (1)
237 #endif
238 
239 #ifndef dg_configUSE_HW_GPIO
240 #define dg_configUSE_HW_GPIO (1)
241 #endif
242 
243 #ifndef dg_configUSE_HW_HASH
244 #define dg_configUSE_HW_HASH (0)
245 #endif
246 
247 #ifndef dg_configUSE_HW_I2C
248 #define dg_configUSE_HW_I2C (0)
249 #endif
250 
251 #ifndef dg_configUSE_HW_MPU
252 #define dg_configUSE_HW_MPU (0)
253 #endif
254 
255 #ifndef dg_configUSE_HW_PCM
256 #define dg_configUSE_HW_PCM (0)
257 #endif
258 
259 #ifndef dg_configUSE_HW_PD
260 #define dg_configUSE_HW_PD (1)
261 #endif
262 
263 #ifndef dg_configUSE_HW_PDC
264 #define dg_configUSE_HW_PDC (1)
265 #endif
266 
267 #ifndef dg_configUSE_HW_PDM
268 #define dg_configUSE_HW_PDM (0)
269 #endif
270 
271 #ifndef dg_configUSE_HW_PMU
272 #define dg_configUSE_HW_PMU (1)
273 #endif
274 
275 #ifndef dg_configUSE_HW_QSPI
276 #if (dg_configCODE_LOCATION == NON_VOLATILE_IS_QSPI_FLASH)
277 #define dg_configUSE_HW_QSPI (1)
278 #elif ( (dg_configCODE_LOCATION == NON_VOLATILE_IS_EMBEDDED_FLASH) || (dg_configCODE_LOCATION == NON_VOLATILE_IS_NONE) )
279 #define dg_configUSE_HW_QSPI (0)
280 #endif
281 #endif
282 
283 #ifndef dg_configUSE_HW_QUAD
284 #define dg_configUSE_HW_QUAD (0)
285 #endif
286 
287 #if (dg_configQSPI_AUTOMODE_ENABLE == 1) && (dg_configUSE_HW_QSPI == 0)
288 # error "Enabling dg_configQSPI_AUTOMODE_ENABLE requires to set dg_configUSE_HW_QSPI"
289 #endif
290 
291 #if (dg_configQSPI_FLASH_AUTODETECT == 1) && (dg_configQSPI_FLASH_CONFIG_VERIFY == 1)
292 # error "dg_configQSPI_FLASH_AUTODETECT and dg_configQSPI_FLASH_CONFIG_VERIFY are mutually exclusive"
293 #endif
294 
295 #ifndef dg_configUSE_HW_QSPI2
296 #define dg_configUSE_HW_QSPI2 (0)
297 #endif
298 
299 #ifndef dg_configUSE_HW_RTC
300 #define dg_configUSE_HW_RTC (1)
301 #endif
302 
303 #ifndef dg_configUSE_HW_SDADC
304 #define dg_configUSE_HW_SDADC (0)
305 #endif
306 
307 
308 #ifndef dg_configUSE_HW_SMOTOR
309 #define dg_configUSE_HW_SMOTOR (0)
310 #endif
311 
312 #ifndef dg_configUSE_HW_SPI
313 #define dg_configUSE_HW_SPI (0)
314 #endif
315 
316 #ifndef dg_configUSE_HW_SRC
317 #define dg_configUSE_HW_SRC (0)
318 #endif
319 
320 #ifndef dg_configUSE_HW_SYS
321 #define dg_configUSE_HW_SYS (1)
322 #endif
323 
324 #ifndef dg_configUSE_HW_TIMER
325 #define dg_configUSE_HW_TIMER (1)
326 #endif
327 
328 #ifndef dg_configUSE_HW_UART
329 #define dg_configUSE_HW_UART (1)
330 #endif
331 
332 #ifndef dg_configUSE_HW_WKUP
333 #define dg_configUSE_HW_WKUP (1)
334 #endif
335 
336 #ifndef dg_configUSE_HW_FCU
337 #define dg_configUSE_HW_FCU (1)
338 #endif
339 
340 #ifndef dg_configGPADC_DMA_SUPPORT
341 # if dg_configUSE_HW_GPADC
342 # define dg_configGPADC_DMA_SUPPORT dg_configUSE_HW_DMA
343 # else
344 # define dg_configGPADC_DMA_SUPPORT (0)
345 # endif
346 #endif
347 
348 #if (dg_configGPADC_DMA_SUPPORT == 1) && ((dg_configUSE_HW_GPADC == 0) || (dg_configUSE_HW_DMA == 0))
349 # pragma message "DMA support for GPADC needs both dg_configUSE_HW_GPADC and dg_configUSE_HW_DMA to be 1"
350 #endif
351 
352 #ifndef dg_configSDADC_DMA_SUPPORT
353 # if dg_configUSE_HW_SDADC
354 # define dg_configSDADC_DMA_SUPPORT dg_configUSE_HW_DMA
355 # else
356 # define dg_configSDADC_DMA_SUPPORT (0)
357 # endif
358 #endif
359 
360 #if (dg_configSDADC_DMA_SUPPORT == 1) && ((dg_configUSE_HW_SDADC == 0) || (dg_configUSE_HW_DMA == 0))
361 # pragma message "DMA support for SDADC needs both dg_configUSE_HW_SDADC and dg_configUSE_HW_DMA to be 1"
362 #endif
363 
364 #ifndef dg_configI2C_DMA_SUPPORT
365 # if dg_configUSE_HW_I2C
366 # define dg_configI2C_DMA_SUPPORT dg_configUSE_HW_DMA
367 # else
368 # define dg_configI2C_DMA_SUPPORT (0)
369 # endif
370 #endif
371 
372 #if (dg_configI2C_DMA_SUPPORT == 1) && ((dg_configUSE_HW_I2C == 0) || (dg_configUSE_HW_DMA == 0))
373 # pragma message "DMA support for I2C needs both dg_configUSE_HW_I2C and dg_configUSE_HW_DMA to be 1"
374 #endif
375 
376 #ifndef dg_configSPI_DMA_SUPPORT
377 # if dg_configUSE_HW_SPI
378 # define dg_configSPI_DMA_SUPPORT dg_configUSE_HW_DMA
379 # else
380 # define dg_configSPI_DMA_SUPPORT (0)
381 # endif
382 #endif
383 
384 #if (dg_configSPI_DMA_SUPPORT == 1) && ((dg_configUSE_HW_SPI == 0) || (dg_configUSE_HW_DMA == 0))
385 # pragma message "DMA support for SPI needs both dg_configUSE_HW_SPI and dg_configUSE_HW_DMA to be 1"
386 #endif
387 
392 /* ------------------------------- Clock Settings ----------------------------------------------- */
393 
400 #if (dg_configUSE_LP_CLK != LP_CLK_32000) && (dg_configUSE_LP_CLK != LP_CLK_32768) && (dg_configUSE_LP_CLK != LP_CLK_RCX) && (dg_configUSE_LP_CLK != LP_CLK_ANY)
401 #error "dg_configUSE_LP_CLK has invalid setting"
402 #endif
403 
404 #if (dg_configUSE_LP_CLK == LP_CLK_ANY)
405 #pragma message "In order to support the option LP_CLK_ANY for the low-power clock source, "\
406  "some configuration options MUST be defined by the application, including "\
407  "dg_configMIN_SLEEP_TIME, dg_configIMAGE_COPY_TIME, dg_configPM_MAX_ADAPTER_DEFER_TIME, "\
408  "TICK_PERIOD, BLE_WUP_LATENCY, sleep_duration_in_lp_cycles and rwip_check_wakeup_boundary. "
409 #pragma message "Additionally, some device-specific configuration options MUST be defined by the application, "\
410  "including dg_configXTAL32K_FREQ."
411 #endif
412 
413 #ifndef dg_configXTAL32M_FREQ
414 #define dg_configXTAL32M_FREQ (32000000)
415 #endif
416 
417 #ifndef dg_configRC32M_FREQ
418 #define dg_configRC32M_FREQ (32000000)
419 #endif
420 
421 #ifndef dg_configRC32M_FREQ_MIN
422 #define dg_configRC32M_FREQ_MIN (30000000)
423 #endif
424 
425 #ifndef dg_configDIVN_FREQ
426 #define dg_configDIVN_FREQ (32000000)
427 #endif
428 
429 #ifndef dg_configDBLR64M_FREQ
430 #define dg_configDBLR64M_FREQ (64000000)
431 #endif
432 
433 #if dg_configUSE_LP_CLK == LP_CLK_32768
434 # undef dg_configXTAL32K_FREQ
435 # define dg_configXTAL32K_FREQ (32768)
436 #elif dg_configUSE_LP_CLK == LP_CLK_32000
437 # undef dg_configXTAL32K_FREQ
438 # define dg_configXTAL32K_FREQ (32000)
439 #elif dg_configUSE_LP_CLK == LP_CLK_RCX
440 # undef dg_configXTAL32K_FREQ
441 # define dg_configXTAL32K_FREQ (0)
442 #endif
443 
449 #ifndef dg_configRC32K_FREQ
450 #define dg_configRC32K_FREQ (32000)
451 #endif
452 
457 #ifndef dg_configLP_CLK_DRIFT
458 # if dg_configUSE_LP_CLK == LP_CLK_RCX
459 # define dg_configLP_CLK_DRIFT (500) //ppm
460 # else
461 # define dg_configLP_CLK_DRIFT (50) //ppm
462 # endif
463 #endif
464 
470 #ifndef dg_configXTAL32K_SETTLE_TIME
471 # if dg_configLP_CLK_SOURCE == LP_CLK_IS_ANALOG
472 # define dg_configXTAL32K_SETTLE_TIME (8000)
473 # else
474 # define dg_configXTAL32K_SETTLE_TIME (1000)
475 # endif
476 #endif
477 
493 #ifndef dg_configXTAL32M_SETTLE_TIME_IN_USEC
494 #define dg_configXTAL32M_SETTLE_TIME_IN_USEC (0x0)
495 #endif
496 
503 #ifndef dg_configENABLE_XTAL32M_ON_WAKEUP
504 #define dg_configENABLE_XTAL32M_ON_WAKEUP (1)
505 #endif
506 
515 #define dg_configWAKEUP_NORMAL (300)
516 
524 #define dg_configWAKEUP_FAST (12)
525 
529 #ifndef dg_configDEFAULT_CLK_RC32M_REG_RC32M_BIAS__VALUE
530 #define dg_configDEFAULT_CLK_RC32M_REG_RC32M_BIAS__VALUE (0xD)
531 #endif
532 
533 #ifndef dg_configDEFAULT_CLK_RC32M_REG_RC32M_RANGE__VALUE
534 #define dg_configDEFAULT_CLK_RC32M_REG_RC32M_RANGE__VALUE (0x1)
535 #endif
536 
537 #ifndef dg_configDEFAULT_CLK_RC32M_REG_RC32M_COSC__VALUE
538 #define dg_configDEFAULT_CLK_RC32M_REG_RC32M_COSC__VALUE (0x4)
539 #endif
540 
544 #ifndef dg_configDEFAULT_XTAL32M_TRIM_REG__XTAL32M_TRIM__VALUE
545 #define dg_configDEFAULT_XTAL32M_TRIM_REG__XTAL32M_TRIM__VALUE (0x45)
546 #endif
547 
548 #ifndef dg_configUSE_CLOCK_MGR
549 # ifdef OS_BAREMETAL
550 # define dg_configUSE_CLOCK_MGR (0)
551 # elif defined(OS_FREERTOS)
552 # define dg_configUSE_CLOCK_MGR (1)
553 # endif
554 #endif
555 
560 /* ------------------------------- System configuration settings -------------------------------- */
561 
568 #if (dg_configUSE_WDOG == 0) && defined(dg_configWDOG_IDLE_RESET_VALUE)
569 # pragma message "dg_configWDOG_IDLE_RESET_VALUE is ignored. Maximum watchdog value will be used."
570 # undef dg_configWDOG_IDLE_RESET_VALUE
571 #endif
572 
576 #ifndef dg_configWDOG_IDLE_RESET_VALUE
577 #define dg_configWDOG_IDLE_RESET_VALUE (SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk >> SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Pos)
578 #endif
579 
589 #ifndef dg_configWDOG_MAX_TASKS_CNT
590 #define dg_configWDOG_MAX_TASKS_CNT (8)
591 #endif
592 
601 #ifndef dg_configWDOG_GUARD_IDLE_TASK
602 #define dg_configWDOG_GUARD_IDLE_TASK (1)
603 #endif
604 
630 #ifndef dg_configSYS_DBG_LOG_PROTECTION
631 # if (!dg_configUSE_CONSOLE)
632 # define dg_configSYS_DBG_LOG_PROTECTION (1)
633 # endif
634 #endif
635 
636 /* The system debug logging protection mechanism does not support M33 baremetal build configurations. */
637 #if (dg_configSYS_DBG_LOG_PROTECTION == 1)
638 # ifdef OS_BAREMETAL
639 # undef dg_configSYS_DBG_LOG_PROTECTION
640 # define dg_configSYS_DBG_LOG_PROTECTION (0)
641 # endif
642 #endif
643 
644 /* Maximum number of characters of a debug logging string that can be printed at a time. A set of chars is
645  * also reserved for printing the processing unit prefix where the string originated from. If the string
646  * is greater in length than the maximum characters minus the prefix then an error message is displayed
647  * instead. This prefix related limitation does not apply for single processing unit applications. */
648 #if dg_configSYS_DBG_LOG_PROTECTION
649 # define dg_configSYS_DBG_LOG_MAX_SIZE 200
650 #endif
651 
665 #ifndef dg_configREDUCE_RETAINED_CODE
666 #if (dg_configCODE_LOCATION == NON_VOLATILE_IS_EMBEDDED_FLASH)
667 #define dg_configREDUCE_RETAINED_CODE (1)
668 #else
669 #define dg_configREDUCE_RETAINED_CODE (0)
670 #endif
671 #endif
672 
673 
674 /*
675  * \brief When set to 1, PD_COM is enabled by power manager when Cortex-M33 master is active. This allows
676  * the master to have access to I2C, SPI, UART and SDADC interfaces, GPIO multiplexing and Timer4.
677  * When set to 0, PD_COM can be enabled by the adapters or the application. PDC can also be configured to
678  * enable PD_COM by setting the appropriate flag in the PDC LUT entry.
679  *
680  * \note In case this macro is disabled, it is application responsibility to apply PD_COM trim and preferred settings
681  * after enabling the power domain.
682  *
683  * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only}
684  */
685 #ifndef dg_configPM_ENABLES_PD_COM_WHILE_ACTIVE
686 #define dg_configPM_ENABLES_PD_COM_WHILE_ACTIVE (1)
687 #endif
688 
693 /* -------------------------------------- Flash settings ---------------------------------------- */
694 
709 #if (dg_configCODE_LOCATION == NON_VOLATILE_IS_QSPI_FLASH)
710 # ifndef dg_configFLASH_CONNECTED_TO
711 # error "dg_configFLASH_CONNECTED_TO is not defined!"
712 # endif
713 #endif
714 
721 #ifndef dg_configPOWER_1V8_ACTIVE
722 # define dg_configPOWER_1V8_ACTIVE (2)
723 #else
724 # if (dg_configPOWER_1V8_ACTIVE == 0) && (dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8)
725 # error "Flash is connected to the 1V8 rail but the rail is turned off. Please do not set dg_configPOWER_1V8_ACTIVE to 0."
726 # endif
727 #endif
728 
735 #ifndef dg_configPOWER_1V8_SLEEP
736 #define dg_configPOWER_1V8_SLEEP (2)
737 #endif
738 
745 #ifndef dg_configQSPI_FLASH_POWER_DOWN
746 #define dg_configQSPI_FLASH_POWER_DOWN (1)
747 #endif
748 
756 #ifndef dg_configQSPI_DRIVE_CURRENT
757 #define dg_configQSPI_DRIVE_CURRENT (HW_QSPI_DRIVE_CURRENT_4)
758 #endif
759 
767 #ifndef dg_configQSPI_SLEW_RATE
768 #define dg_configQSPI_SLEW_RATE (HW_QSPI_SLEW_RATE_0)
769 #endif
770 
776 #ifndef dgconfigQSPI_ERASE_IN_AUTOMODE
777 #define dgconfigQSPI_ERASE_IN_AUTOMODE (1)
778 #endif
779 
780 #if (dg_configQSPI_FLASH_AUTODETECT == 0)
781 
789 #ifndef dg_configQSPI_FLASH_HEADER_FILE
790 #define dg_configQSPI_FLASH_HEADER_FILE "qspi_mx25u3235_v2.h"
791 #endif /* dg_configQSPI_FLASH_HEADER_FILE */
792 
800 #ifndef dg_configQSPI_FLASH_CONFIG
801 #define dg_configQSPI_FLASH_CONFIG qspi_mx25u3235_cfg
802 #endif /* dg_configQSPI_FLASH_CONFIG */
803 
814 #ifndef dg_configQSPI_FLASH_CONFIG_VERIFY
815 #define dg_configQSPI_FLASH_CONFIG_VERIFY (0)
816 #endif
817 #endif /* (dg_configQSPI_FLASH_AUTODETECT == 0) */
818 
826 #ifndef dg_configEFLASH_MASS_ERASE_TIME
827 #define dg_configEFLASH_MASS_ERASE_TIME 160000
828 #endif
829 
837 #ifndef dg_configEFLASH_PAGE_ERASE_TIME
838 #define dg_configEFLASH_PAGE_ERASE_TIME 160000
839 #endif
840 
848 #ifndef dg_configEFLASH_WORD_WRITE_TIME
849 #define dg_configEFLASH_WORD_WRITE_TIME 16
850 #endif
851 
873 #ifndef dg_configHW_FCU_WAIT_CYCLES_MODE
874 #if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE)
875 #define dg_configHW_FCU_WAIT_CYCLES_MODE (2)
876 #else
877 #define dg_configHW_FCU_WAIT_CYCLES_MODE (1)
878 #endif /* dg_configIMAGE_SETUP */
879 #endif /* dg_configHW_FCU_WAIT_CYCLES_MODE */
880 
885 /* ----------------------------------- Charger settings ----------------------------------------- */
886 
898 #ifndef dg_configUSE_SOC
899 #define dg_configUSE_SOC (0)
900 #endif
901 
906 /* ----------------------------------- UART settings -------------------------------------------- */
907 
913 #ifndef dg_configUART_DMA_SUPPORT
914 # if dg_configUSE_HW_UART
915 # define dg_configUART_DMA_SUPPORT dg_configUSE_HW_DMA
916 # else
917 # define dg_configUART_DMA_SUPPORT (0)
918 # endif
919 #endif
920 
921 #if (dg_configUART_DMA_SUPPORT == 1) && ((dg_configUSE_HW_UART == 0) || (dg_configUSE_HW_DMA == 0))
922 # pragma message "DMA support for UART needs both dg_configUSE_HW_UART and dg_configUSE_HW_DMA to be 1"
923 #endif
924 
925 #if (dg_configUART_RX_CIRCULAR_DMA == 1) && (dg_configUART_DMA_SUPPORT == 0)
926 #error "dg_configUART_RX_CIRCULAR_DMA requires dg_configUART_DMA_SUPPORT to be enabled!"
927 #endif
928 
933 /* ----------------------------------- MPU settings -------------------------------------------- */
934 
941 #if defined(CONFIG_USE_BLE)
942 
947 #ifndef dg_configCMAC_PROTECT_REGION
948 #define dg_configCMAC_PROTECT_REGION MPU_REGION_6
949 #endif
950 #endif /* CONFIG_USE_BLE */
951 
957 #ifndef dg_configIVT_PROTECT_REGION
958 #define dg_configIVT_PROTECT_REGION MPU_REGION_7
959 #endif
960 
965 /*
966  */
967 /*------------------------------------ BOARDS DEFINITIONS ----------------------------------------*/
968 
972 #ifndef dg_configUSE_BOARD
973 # include "boards/brd_prodk_da1459x.h"
974 # define dg_configUSE_BOARD
975 #endif
976 
977 
978 #endif /* BSP_DEFAULTS_DA1459X_H_ */
979 
brd_prodk_da1459x.h
Board Support Package. DA1459x Board I/O configuration.
Generated on Tue Oct 24 2023 10:38:23 for SmartSnippets DA1459x SDK by   doxygen 1.8.16