SmartSnippets DA1459x SDK
qspi_w25q32jwiq_v2.h
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1 
42 #ifndef _QSPI_W25Q32JWIQ_V2_H_
43 #define _QSPI_W25Q32JWIQ_V2_H_
44 
45 #include "hw_clk.h"
46 #include "hw_qspi.h"
47 #include "qspi_common.h"
48 #include "qspi_winbond_v2.h"
49 
50 #define QSPI_W25Q32JWIQ_DENSITY (0x16)
51 
52 __RETAINED_CODE static void qspi_w25q32jwiq_initialize(HW_QSPIC_ID id, sys_clk_t sys_clk);
53 
54 static const qspi_flash_config_t qspi_w25q32jwiq_cfg = {
55  .jedec.manufacturer_id = QSPI_WINBOND_MANUFACTURER_ID,
56  .jedec.type = QSPI_WINBOND_W25QXXXJWIQ_TYPE,
57  .jedec.density = QSPI_W25Q32JWIQ_DENSITY,
58  .jedec.density_mask = 0xFF,
59 
60  .size_bits = QSPI_MEMORY_SIZE_32Mbits,
61  .address_size = HW_QSPI_ADDR_SIZE_24,
62  .clk_mode = HW_QSPI_CLK_MODE_LOW,
63 
64  .read_instr_cfg.opcode_bus_mode = HW_QSPI_BUS_MODE_SINGLE,
65  .read_instr_cfg.addr_bus_mode = HW_QSPI_BUS_MODE_QUAD,
66  .read_instr_cfg.extra_byte_bus_mode = HW_QSPI_BUS_MODE_QUAD,
67  .read_instr_cfg.dummy_bus_mode = HW_QSPI_BUS_MODE_QUAD,
68  .read_instr_cfg.data_bus_mode = HW_QSPI_BUS_MODE_QUAD,
69  // This memory doesn't support continuous mode of operation
70  .read_instr_cfg.continuous_mode = HW_QSPI_CONTINUOUS_MODE_DISABLE,
71  .read_instr_cfg.extra_byte_cfg = HW_QSPI_EXTRA_BYTE_ENABLE,
72  .read_instr_cfg.extra_byte_half_cfg = HW_QSPI_EXTRA_BYTE_HALF_DISABLE,
73  .read_instr_cfg.opcode = QSPI_FAST_READ_QUAD_OPCODE,
74  .read_instr_cfg.extra_byte_value = 0xFF,
75  .read_instr_cfg.cs_idle_delay_nsec = 10, // tSHSL1
76 
77  .erase_instr_cfg.opcode_bus_mode = HW_QSPI_BUS_MODE_SINGLE,
78  .erase_instr_cfg.addr_bus_mode = HW_QSPI_BUS_MODE_SINGLE,
79  .erase_instr_cfg.hclk_cycles = 0,
80  .erase_instr_cfg.opcode = QSPI_SECTOR_ERASE_OPCODE,
81  .erase_instr_cfg.cs_idle_delay_nsec = 50, // tSHSL2
82 
83  .read_status_instr_cfg.opcode_bus_mode = HW_QSPI_BUS_MODE_SINGLE,
84  .read_status_instr_cfg.receive_bus_mode = HW_QSPI_BUS_MODE_SINGLE,
85  .read_status_instr_cfg.busy_level = HW_QSPI_BUSY_LEVEL_HIGH,
86  .read_status_instr_cfg.busy_pos = QSPI_STATUS_REG_BUSY_BIT,
87  .read_status_instr_cfg.opcode = QSPI_READ_STATUS_REG_OPCODE,
88  .read_status_instr_cfg.delay_nsec = 0,
89 
90  .write_enable_instr_cfg.opcode_bus_mode = HW_QSPI_BUS_MODE_SINGLE,
91  .write_enable_instr_cfg.opcode = QSPI_WRITE_ENABLE_OPCODE,
92 
93  .page_program_instr_cfg.opcode_bus_mode = HW_QSPI_BUS_MODE_SINGLE,
94  .page_program_instr_cfg.addr_bus_mode = HW_QSPI_BUS_MODE_SINGLE,
95  .page_program_instr_cfg.data_bus_mode = HW_QSPI_BUS_MODE_QUAD,
96  .page_program_instr_cfg.opcode = QSPI_PAGE_PROGRAM_QUAD_OPCODE,
97 
98  .suspend_resume_instr_cfg.suspend_bus_mode = HW_QSPI_BUS_MODE_SINGLE,
99  .suspend_resume_instr_cfg.resume_bus_mode = HW_QSPI_BUS_MODE_SINGLE,
100  .suspend_resume_instr_cfg.suspend_opcode = QSPI_WINBOND_SUSPEND_OPCODE,
101  .suspend_resume_instr_cfg.resume_opcode = QSPI_WINBOND_RESUME_OPCODE,
102  .suspend_resume_instr_cfg.resume_latency_usec = 1, // 200 nsec
103  .suspend_resume_instr_cfg.res_sus_latency_usec = 20, // tSUS
104 
105  .delay.reset_usec = 30, // tRST
106  .delay.power_down_usec = 3, // tDP
107  .delay.release_power_down_usec = 30, // tRES1
108  .delay.power_up_usec = 20, // tVSL
109 
110  .callback.initialize_cb = qspi_w25q32jwiq_initialize,
111  .callback.sys_clk_cfg_cb = qspi_winbond_sys_clock_cfg,
112  .callback.exit_qpi_cb = qspi_exit_qpi,
113  .callback.get_dummy_bytes_cb = qspi_winbond_get_dummy_bytes,
114  .callback.is_suspended_cb = qspi_winbond_is_suspended,
115  .callback.is_busy_cb = qspi_winbond_is_busy,
116  .callback.read_status_reg_cb = qspi_winbond_read_status_reg,
117  .callback.write_status_reg_cb = qspi_winbond_write_status_reg,
118 
119  .resume_before_writing_regs = false,
120 };
121 
122 __RETAINED_CODE static void qspi_w25q32jwiq_initialize(HW_QSPIC_ID id, sys_clk_t sys_clk)
123 {
124 #if QSPI_WINBOND_UNLOCK_PROTECTION
125  qspi_winbond_unlock_protection(id);
126 #endif
127 
128  // The Quad Enable (QE) bit of this flash memory is enabled by default as a fixed setting
129  // from the factory. Nevertheless, the function qspi_winbond_enable_quad_mode() is invoked
130  // to ensure that the QE bit is enabled.
131  qspi_winbond_enable_quad_mode(id);
132 }
133 
134 #if (dg_configCODE_LOCATION == NON_VOLATILE_IS_QSPI_FLASH) & (dg_configQSPI_FLASH_AUTODETECT == 0)
135 __attribute__((used, __section__("__product_header_primary__")))
136 static const PRODUCT_HEADER_STRUCT(3) ph_primary = {
137  .burstcmdA = 0xA8FF00EB,
138  .burstcmdB = 0x00001026,
139  .flash_config_section = 0x11AA,
140  .flash_config_length = 0x3,
141  .config_seq = {0x31, 0x02, 0x02},
142  .crc = 0xE264
143 };
144 
145 __attribute__((used, __section__("__product_header_backup__")))
146 static const PRODUCT_HEADER_STRUCT(3) ph_backup = {
147  .burstcmdA = 0xA8FF00EB,
148  .burstcmdB = 0x00001026,
149  .flash_config_section = 0x11AA,
150  .flash_config_length = 0x3,
151  .config_seq = {0x31, 0x02, 0x02},
152  .crc = 0xE264
153 };
154 #endif /* (dg_configUSE_SEGGER_FLASH_LOADER == 1) && (dg_configFLASH_AUTODETECT == 0) */
155 
156 #endif /* _QSPI_W25Q32JWIQ_V2_H_ */
157 
qspi_winbond_v2.h
The macros and functions of this header file are utilized by the memory drivers of the Winbond QSPI f...
HW_QSPI_ADDR_SIZE_24
Definition: hw_qspi_v2.h:69
HW_QSPIC_ID
void * HW_QSPIC_ID
QSPI Controller ID.
Definition: hw_qspi_v2.h:439
qspi_flash_config_t::jedec
jedec_id_t jedec
Definition: qspi_common_v2.h:167
HW_QSPI_EXTRA_BYTE_ENABLE
Definition: hw_qspi_v2.h:141
HW_QSPI_BUS_MODE_QUAD
Definition: hw_qspi_v2.h:79
HW_QSPI_BUS_MODE_SINGLE
Definition: hw_qspi_v2.h:77
sys_clk_t
enum sysclk_type sys_clk_t
The system clock type.
jedec_id_t::manufacturer_id
uint8_t manufacturer_id
Definition: qspi_common_v2.h:120
__attribute__
__attribute__
Definition: suota_security_ext.h:98
HW_QSPI_CLK_MODE_LOW
Definition: hw_qspi_v2.h:113
HW_QSPI_EXTRA_BYTE_HALF_DISABLE
Definition: hw_qspi_v2.h:150
HW_QSPI_CONTINUOUS_MODE_DISABLE
Definition: hw_qspi_v2.h:121
HW_QSPI_BUSY_LEVEL_HIGH
Definition: hw_qspi_v2.h:96
hw_qspi.h
Low Level Driver of QSPI controllers.
hw_clk.h
Clock Driver header file.
qspi_common.h
QSPI flash driver common definitions.
qspi_flash_config_t
QSPI memory configuration structure.
Definition: qspi_common_v2.h:166
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