SPI configuration. More...

#include <hw_spi.h>

Data Fields
SPI_Pad	cs_pad

HW_SPI_WORD	word_mode

HW_SPI_MODE	smn_role

HW_SPI_MODE_CPOL_CPHA	cpol_cpha_mode

HW_SPI_FREQ	xtal_freq

HW_SPI_FIFO	fifo_mode

uint8_t	disabled

HW_SPI_CS_MODE	spi_cs

HW_SPI_FIFO_TL	rx_tl

HW_SPI_FIFO_TL	tx_tl

bool	swap_bytes

bool	select_divn

Detailed Description

SPI configuration.

Field Documentation

◆ cpol_cpha_mode

HW_SPI_MODE_CPOL_CPHA hw_spi_config_t::cpol_cpha_mode

Configure clock polarity and phase

◆ cs_pad

SPI_Pad hw_spi_config_t::cs_pad

Configure SPI chip-select pin

◆ disabled

uint8_t hw_spi_config_t::disabled

Configure SPI (enable/disable) at initialization

◆ fifo_mode

HW_SPI_FIFO hw_spi_config_t::fifo_mode

Configure SPI fifo mode at initialization

◆ rx_tl

HW_SPI_FIFO_TL hw_spi_config_t::rx_tl

Configure FIFO_RX_TL. Note: in case DMA is used, rx_tl should be 0

◆ select_divn

bool hw_spi_config_t::select_divn

Configure DIVN

◆ smn_role

HW_SPI_MODE hw_spi_config_t::smn_role

Configure SPI master/slave mode

◆ spi_cs

HW_SPI_CS_MODE hw_spi_config_t::spi_cs

Configure the CS output in master mode

◆ swap_bytes

bool hw_spi_config_t::swap_bytes

Configure to change endianness in APB interface or not

◆ tx_tl

HW_SPI_FIFO_TL hw_spi_config_t::tx_tl

Configure FIFO_TX_TL

◆ word_mode

HW_SPI_WORD hw_spi_config_t::word_mode

Configure SPI word length

◆ xtal_freq

HW_SPI_FREQ hw_spi_config_t::xtal_freq

Configure the clock divider applied to the clock source which defines the SPI clock frequency

The documentation for this struct was generated from the following file:

sdk/bsp/peripherals/include/hw_spi.h

Data Fields