hw_cache.h

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#ifndef HW_CACHE_H_
#define HW_CACHE_H_
 
#if dg_configUSE_HW_CACHE
 
#include <sdk_defs.h>
 
        #include "hw_cache_da1459x.h"
 
/*
 * COMMON API MRM RELATED FUNCTIONALITY DEFINITIONS
 *****************************************************************************************
 */
 
__STATIC_INLINE void hw_cache_mrm_set_misses_thres(uint32_t thres)
{
        CACHE->CACHE_MRM_MISSES_THRES_REG = thres;
}
 
__STATIC_INLINE uint32_t hw_cache_mrm_get_misses_thres(void)
{
        return CACHE->CACHE_MRM_MISSES_THRES_REG;
}
 
__STATIC_INLINE void hw_cache_mrm_set_hits_thres(uint32_t thres)
{
        CACHE->CACHE_MRM_HITS_THRES_REG = thres;
}
 
__STATIC_INLINE uint32_t hw_cache_mrm_get_hits_thres(void)
{
        return CACHE->CACHE_MRM_HITS_THRES_REG;
}
 
__STATIC_INLINE bool hw_cache_mrm_get_misses_thres_status(void)
{
        return REG_GETF(CACHE, CACHE_MRM_CTRL_REG, MRM_IRQ_MISSES_THRES_STATUS);
}
 
__STATIC_INLINE void hw_cache_mrm_clr_misses_thres_status(void)
{
        REG_CLR_BIT(CACHE, CACHE_MRM_CTRL_REG, MRM_IRQ_MISSES_THRES_STATUS);
}
 
__STATIC_INLINE bool hw_cache_mrm_get_hits_thres_status(void)
{
        return REG_GETF(CACHE, CACHE_MRM_CTRL_REG, MRM_IRQ_HITS_THRES_STATUS);
}
 
__STATIC_INLINE void hw_cache_mrm_clr_hits_thres_status(void)
{
        REG_CLR_BIT(CACHE, CACHE_MRM_CTRL_REG, MRM_IRQ_HITS_THRES_STATUS);
}
 
__STATIC_INLINE void hw_cache_mrm_set_tint(uint32_t tint)
{
        ASSERT_WARNING((tint & ~CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk) == 0)
                CACHE->CACHE_MRM_TINT_REG = tint;
}
 
__STATIC_INLINE uint32_t hw_cache_mrm_get_tint(void)
{
        return CACHE->CACHE_MRM_TINT_REG & CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk;
}
 
__STATIC_INLINE bool hw_cache_mrm_get_tint_status(void)
{
        return REG_GETF(CACHE, CACHE_MRM_CTRL_REG, MRM_IRQ_TINT_STATUS);
}
 
__STATIC_INLINE void hw_cache_mrm_clr_tint_status(void)
{
        REG_CLR_BIT(CACHE, CACHE_MRM_CTRL_REG, MRM_IRQ_TINT_STATUS);
}
 
__STATIC_INLINE void hw_cache_mrm_start_counters(void)
{
        REG_SET_BIT(CACHE, CACHE_MRM_CTRL_REG, MRM_START);
}
 
__STATIC_INLINE void hw_cache_mrm_freeze_counters(void)
{
        REG_CLR_BIT(CACHE, CACHE_MRM_CTRL_REG, MRM_START);
}
 
__STATIC_INLINE uint32_t hw_cache_mrm_get_misses(void)
{
        return CACHE->CACHE_MRM_MISSES_REG;
}
 
__STATIC_INLINE void hw_cache_mrm_set_misses(uint32_t misses)
{
        CACHE->CACHE_MRM_MISSES_REG = misses;
}
 
__STATIC_INLINE uint32_t hw_cache_mrm_get_hits(void)
{
        return CACHE->CACHE_MRM_HITS_REG;
}
 
__STATIC_INLINE void hw_cache_mrm_set_hits(uint32_t hits)
{
        CACHE->CACHE_MRM_HITS_REG = hits;
}
 
typedef void (*hw_cache_mrm_cb_t)(void);
 
void hw_cache_mrm_enable_interrupt(hw_cache_mrm_cb_t cb);
 
void hw_cache_mrm_disable_interrupt(void);
 
#endif /* dg_configUSE_HW_CACHE */
 
#endif /* HW_CACHE_H_ */