NVIC_Type Struct Reference

Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...

#include <core_cm0.h>

Data Fields
__IOM uint32_t	ISER [1U]
__IOM uint32_t	ICER [1U]
__IOM uint32_t	ISPR [1U]
__IOM uint32_t	ICPR [1U]
__IOM uint32_t	IP [8U]
__IOM uint32_t	IABR [16U]
__IOM uint32_t	ITNS [16U]
__IOM uint8_t	IPR [496U]
__OM uint32_t	STIR

Detailed Description

Structure type to access the Nested Vectored Interrupt Controller (NVIC).

Field Documentation

IABR

__IOM uint32_t NVIC_Type::IABR[16U]

Offset: 0x200 (R/W) Interrupt Active bit Register

ICER

__IOM uint32_t NVIC_Type::ICER

Offset: 0x080 (R/W) Interrupt Clear Enable Register

ICPR

__IOM uint32_t NVIC_Type::ICPR

Offset: 0x180 (R/W) Interrupt Clear Pending Register

IP

__IOM uint32_t NVIC_Type::IP[8U]

Offset: 0x300 (R/W) Interrupt Priority Register

IPR

__IOM uint8_t NVIC_Type::IPR[496U]

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

ISER

__IOM uint32_t NVIC_Type::ISER

Offset: 0x000 (R/W) Interrupt Set Enable Register

ISPR

__IOM uint32_t NVIC_Type::ISPR

Offset: 0x100 (R/W) Interrupt Set Pending Register

ITNS

__IOM uint32_t NVIC_Type::ITNS[16U]

Offset: 0x280 (R/W) Interrupt Non-Secure State Register

STIR

__OM uint32_t NVIC_Type::STIR

Offset: 0xE00 ( /W) Software Trigger Interrupt Register

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The documentation for this struct was generated from the following files:

• sdk/bsp/include/core_cm0.h
• sdk/bsp/include/core_cm33.h