hw_sys.h

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#ifndef HW_SYS_H_
#define HW_SYS_H_
#if dg_configUSE_HW_SYS
 
#include "sdk_defs.h"
#include "hw_pd.h"
 
#include <hw_memctrl.h>
 
/* \brief Specifies the HW BSR mask used for accessing the SW BSR */
#define SW_BSR_HW_BSR_MASK     (0x3)
 
/*
 * \brief Enumerations used when accessing the HW BSR register
 */
typedef enum {
        HW_BSR_MASTER_NONE = 0,
        HW_BSR_MASTER_SYSCPU = 2,
        HW_BSR_MASTER_CMAC = 3,
        HW_BSR_MASTER_NUM,
} HW_BSR_MASTER_ID;
 
/*
 * \brief HW BSR position
 */
typedef enum {
        HW_BSR_SW_POS = 0,
        HW_BSR_POWER_CTRL_POS = 28,
        HW_BSR_WAKEUP_CONFIG_POS = 30,
} HW_BSR_POS;
 
/*
 * \brief Enumerations used when accessing the SW BSR variable
 */
typedef enum {
        SW_BSR_MASTER_NONE = 1 << HW_BSR_MASTER_NONE,
        SW_BSR_MASTER_SYSCPU = 1 << HW_BSR_MASTER_SYSCPU,
        SW_BSR_MASTER_CMAC = 1 << HW_BSR_MASTER_CMAC,
} SW_BSR_MASTER_ID;
 
typedef enum {
        BSR_PERIPH_ID_SPI = 1,
        BSR_PERIPH_ID_UART1 = 2,
        BSR_PERIPH_ID_UART2 = 3,
        BSR_PERIPH_ID_I2C = 4,
        BSR_PERIPH_ID_GPADC = 5,
        BSR_PERIPH_ID_SDADC = 6,
        BSR_PERIPH_ID_MAX = 14,
} HW_SYS_BSR_PERIPH_ID;
 
typedef struct {
        __IO uint32_t *addr;    
        uint32_t value;         
} hw_sys_reg_config_t;
 
/*
 * Export hw_sys_sw_bsr so that other masters have access to its address.
 */
extern __RETAINED uint32_t hw_sys_sw_bsr[BSR_PERIPH_ID_MAX];
 
typedef enum {
        HW_SYS_REMAP_ADDRESS_0_TO_ROM,
        HW_SYS_REMAP_ADDRESS_0_TO_EFLASH,
        HW_SYS_REMAP_ADDRESS_0_TO_QSPI_FLASH,
        HW_SYS_REMAP_ADDRESS_0_TO_RAM,
} HW_SYS_REMAP_ADDRESS_0;
 
__STATIC_INLINE void hw_sys_set_memory_remapping(HW_SYS_REMAP_ADDRESS_0 value)
{
        GLOBAL_INT_DISABLE();
        REG_SETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0, value);
        GLOBAL_INT_RESTORE();
}
 
__STATIC_INLINE HW_SYS_REMAP_ADDRESS_0 hw_sys_get_memory_remapping(void)
{
        HW_SYS_REMAP_ADDRESS_0 value;
        GLOBAL_INT_DISABLE();
        value = REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0);
        GLOBAL_INT_RESTORE();
        return value;
}
 
__STATIC_INLINE void hw_sys_set_cache_retained(void)
{
        GLOBAL_INT_DISABLE();
        REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RETAIN_CACHE);
        GLOBAL_INT_RESTORE();
}
 
 
__STATIC_INLINE void hw_sys_setup_retmem(void)
{
        GLOBAL_INT_DISABLE();
 
        CRG_TOP->RAM_PWR_CTRL_REG = dg_configMEM_RETENTION_MODE;
 
        GLOBAL_INT_RESTORE();
}
 
__STATIC_INLINE void hw_sys_no_retmem(void)
{
        GLOBAL_INT_DISABLE();
        REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, RETAIN_CACHE);
        CRG_TOP->RAM_PWR_CTRL_REG = RETMEM_RETAIN_NONE;
        GLOBAL_INT_RESTORE();
}
 
__STATIC_FORCEINLINE void hw_sys_track_reset_type(void)
{
        CRG_TOP->RESET_STAT_REG = 0;
}
 
 
__STATIC_INLINE void hw_sys_enable_reset_on_wup(void)
{
        GLOBAL_INT_DISABLE();
        REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RESET_ON_WAKEUP);
        GLOBAL_INT_RESTORE();
}
 
void hw_sys_set_preferred_values(HW_PD pd);
 
void hw_sys_setup_sw_cursor(void);
 
void hw_sys_trigger_sw_cursor(void);
 
__STATIC_FORCEINLINE void hw_sys_enable_debugger(void)
{
        GLOBAL_INT_DISABLE();
        REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE);
        GLOBAL_INT_RESTORE();
}
 
__STATIC_FORCEINLINE void hw_sys_disable_debugger(void)
{
        GLOBAL_INT_DISABLE();
        REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE);
        GLOBAL_INT_RESTORE();
}
 
__STATIC_FORCEINLINE bool hw_sys_is_debugger_attached(void)
{
        return (REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE) != 0);
}
 
 
__STATIC_FORCEINLINE void hw_sys_enable_hibernation(void)
{
        GLOBAL_INT_DISABLE();
        REG_SET_BIT(CRG_TOP, HIBERN_CTRL_REG, HIBERNATION_ENABLE);
        GLOBAL_INT_RESTORE();
}
 
__STATIC_FORCEINLINE void hw_sys_enable_cmac_cache_ram(void)
{
        hw_pd_power_up_rad();
        REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, CMAC_CLK_ENABLE);
}
 
__STATIC_FORCEINLINE void hw_sys_disable_cmac_cache_ram(void)
{
        REG_CLR_BIT(CRG_TOP, CLK_RADIO_REG, CMAC_CLK_ENABLE);
        hw_pd_power_down_rad();
}
 
 
__ALWAYS_RETAINED_CODE void hw_sys_assert_trigger_gpio(void);
 
void hw_sys_enable_cmac_mem_protection(void);
 
void hw_sys_enable_ivt_mem_protection(void);
 
 
__STATIC_FORCEINLINE void hw_sys_set_por_timer(uint8_t time)
{
        ASSERT_WARNING(time <= (REG_MSK(CRG_TOP, POR_TIMER_REG, POR_TIME)
                             >> REG_POS(CRG_TOP, POR_TIMER_REG, POR_TIME)));
        REG_SETF(CRG_TOP, POR_TIMER_REG, POR_TIME, time);
}
 
bool hw_sys_hw_bsr_try_lock(HW_BSR_MASTER_ID hw_bsr_master_id, HW_BSR_POS pos);
 
void hw_sys_hw_bsr_unlock(HW_BSR_MASTER_ID hw_bsr_master_id, HW_BSR_POS pos);
 
void hw_sys_sw_bsr_init(void);
 
bool hw_sys_sw_bsr_try_acquire(SW_BSR_MASTER_ID sw_bsr_master_id, uint32_t periph_id);
 
bool hw_sys_sw_bsr_acquired(SW_BSR_MASTER_ID sw_bsr_master_id, uint32_t periph_id);
 
void hw_sys_sw_bsr_release(SW_BSR_MASTER_ID sw_bsr_master_id, uint32_t periph_id);
 
void hw_sys_pd_com_enable(void);
 
void hw_sys_pd_com_disable(void);
 
void hw_sys_pd_periph_enable(void);
 
void hw_sys_pd_periph_disable(void);
 
__RETAINED_CODE void hw_sys_pd_audio_enable(void);
 
__RETAINED_CODE void hw_sys_pd_audio_disable(void);
 
uint32_t hw_sys_reg_add_config(const hw_sys_reg_config_t *config, uint32_t num_of_entries);
 
hw_sys_reg_config_t *hw_sys_reg_get_config(uint32_t index);
 
void hw_sys_reg_modify_config(uint32_t index, __IO uint32_t *addr, uint32_t value);
 
uint32_t *hw_sys_reg_get_num_of_config_entries(void);
 
__RETAINED_CODE void hw_sys_reg_apply_config(void);
void hw_sys_apply_default_values(void);
 
 
#endif /* dg_configUSE_HW_SYS */
#endif /* HW_SYS_H_ */