qspi_common_v2.h

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#ifndef _QSPI_COMMON_V2_H_
#define _QSPI_COMMON_V2_H_
 
 
#include <stdbool.h>
#include "hw_qspi.h"
 
#if __DBG_QSPI_ENABLED
#define __DBG_QSPI_VOLATILE__           volatile
#pragma message "qspi_automode.{h c} debugging mode enabled"
#else
#define __DBG_QSPI_VOLATILE__
#endif
 
#define QSPI_WRITE_STATUS_REG_OPCODE           (0x01)
#define QSPI_WRITE_DISABLE_OPCODE              (0x04)
#define QSPI_READ_STATUS_REG_OPCODE            (0x05)
#define QSPI_WRITE_ENABLE_OPCODE               (0x06)
#define QSPI_RESET_EN_OPCODE                   (0x66)
#define QSPI_RESET_OPCODE                      (0x99)
#define QSPI_READ3B_OPCODE                     (0x03)
#define QSPI_FAST_READ_QUAD_OPCODE             (0xEB)
#define QSPI_BLOCK_ERASE_OPCODE                (0x52)
#define QSPI_CHIP_ERASE_OPCODE                 (0xC7)
#define QSPI_SECTOR_ERASE_OPCODE               (0x20)
#define QSPI_PAGE_PROGRAM_QPI_OPCODE           (0x02)
#define QSPI_PAGE_PROGRAM_QUAD_OPCODE          (0x32)
#define QSPI_READ_JEDEC_ID_OPCODE              (0x9F)
#define QSPI_EXIT_CONTINUOUS_MODE_BYTE         (0xFF)
#define QSPI_EXIT_CONTINUOUS_MODE_WORD         (0xFFFFFFFF)
 
#define QSPI_RELEASE_POWER_DOWN_OPCODE         (0xAB)
#define QSPI_ENTER_POWER_DOWN_OPCODE           (0xB9)
 
#define QSPI_ENTER_QPI_OPCODE                  (0x38)
#define QSPI_EXIT_QPI_OPCODE                   (0xFF)
 
/* Erase/Write in progress */
#define QSPI_STATUS_REG_BUSY_BIT               (0)
#define QSPI_STATUS_REG_BUSY_MASK              (1 << QSPI_STATUS_REG_BUSY_BIT)
 
/* WE Latch bit */
#define QSPI_STATUS_REG_WEL_BIT                (1)
#define QSPI_STATUS_REG_WEL_MASK               (1 << QSPI_STATUS_REG_WEL_BIT)
 
#define QSPI_MEMORY_SIZE_1Mbit                 (1024 * 1024)
#define QSPI_MEMORY_SIZE_2Mbits                (2 * QSPI_MEMORY_SIZE_1Mbit)
#define QSPI_MEMORY_SIZE_4Mbits                (4 * QSPI_MEMORY_SIZE_1Mbit)
#define QSPI_MEMORY_SIZE_8Mbits                (8 * QSPI_MEMORY_SIZE_1Mbit)
#define QSPI_MEMORY_SIZE_16Mbits               (16 * QSPI_MEMORY_SIZE_1Mbit)
#define QSPI_MEMORY_SIZE_32Mbits               (32 * QSPI_MEMORY_SIZE_1Mbit)
#define QSPI_MEMORY_SIZE_64Mbits               (64 * QSPI_MEMORY_SIZE_1Mbit)
#define QSPI_MEMORY_SIZE_128Mbits              (128 * QSPI_MEMORY_SIZE_1Mbit)
#define QSPI_MEMORY_SIZE_256Mbits              (256 * QSPI_MEMORY_SIZE_1Mbit)
#define QSPI_MEMORY_SIZE_512Mbits              (512 * QSPI_MEMORY_SIZE_1Mbit)
#define QSPI_MEMORY_SIZE_1Gbit                 (1024 * QSPI_MEMORY_SIZE_1Mbit)
 
#define PRODUCT_HEADER_STRUCT(_N_) \
__PACKED_STRUCT { \
        uint32_t burstcmdA; \
        uint32_t burstcmdB; \
        uint16_t flash_config_section; \
        uint16_t flash_config_length; \
        uint8_t config_seq[_N_]; \
        uint16_t crc; \
}
 
typedef void (* qspi_initialize_cb_t) (HW_QSPIC_ID id, sys_clk_t sys_clk);
typedef void (* qspi_sys_clk_cfg_cb_t) (HW_QSPIC_ID id, sys_clk_t sys_clk);
typedef bool (* qspi_exit_qpi_cb_t) (HW_QSPIC_ID id);
typedef uint8_t (* qspi_get_dummy_bytes_cb_t) (HW_QSPIC_ID id, sys_clk_t sys_clk);
typedef bool (* qspi_is_suspended_cb_t) (HW_QSPIC_ID id);
typedef bool (* qspi_is_busy_cb_t) (HW_QSPIC_ID id, HW_QSPI_BUSY_LEVEL busy_level);
typedef uint8_t (* qspi_read_status_reg_cb_t) (HW_QSPIC_ID id);
typedef void (* qspi_write_status_reg_cb_t) (HW_QSPIC_ID id, uint8_t value);
 
typedef struct {
        uint8_t         manufacturer_id;        
        uint8_t         type;                   
        uint8_t         density;                
        uint8_t         density_mask;           
} jedec_id_t;
 
typedef struct {
        qspi_initialize_cb_t           initialize_cb;          
        qspi_sys_clk_cfg_cb_t          sys_clk_cfg_cb;         
        qspi_exit_qpi_cb_t             exit_qpi_cb;            
        qspi_get_dummy_bytes_cb_t      get_dummy_bytes_cb;     
        qspi_is_suspended_cb_t         is_suspended_cb;        
        qspi_is_busy_cb_t              is_busy_cb;             
        qspi_read_status_reg_cb_t      read_status_reg_cb;     
        qspi_write_status_reg_cb_t     write_status_reg_cb;    
} qspi_callback_t;
 
typedef struct {
        uint16_t                        reset_usec;             
        uint16_t                        power_down_usec;        
        uint16_t                        release_power_down_usec;
        uint16_t                        power_up_usec;          
} qspi_delay_t;
 
typedef struct {
        jedec_id_t                              jedec;                          
        uint32_t                                size_bits;                      
        HW_QSPI_ADDR_SIZE                       address_size : 1;               
        HW_QSPI_CLK_MODE                        clk_mode : 1;                   
        hw_qspi_read_instr_config_t             read_instr_cfg;                 
        hw_qspi_erase_instr_config_t            erase_instr_cfg;                
        hw_qspi_read_status_instr_config_t      read_status_instr_cfg;          
        hw_qspi_write_enable_instr_config_t     write_enable_instr_cfg;         
        hw_qspi_page_program_instr_config_t     page_program_instr_cfg;         
        hw_qspi_suspend_resume_instr_config_t   suspend_resume_instr_cfg;       
        qspi_delay_t                            delay;                          
        qspi_callback_t                         callback;                       
        bool                                    resume_before_writing_regs;     
} qspi_flash_config_t;
 
 
#endif /* _QSPI_COMMON_V2_H_ */