hw_mpu.h

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#ifndef HW_MPU_H_
#define HW_MPU_H_
 
 
#if dg_configUSE_HW_MPU
 
#include <stdbool.h>
#include "sdk_defs.h"
 
#define MPU_START_ADDRESS_MASK (~MPU_END_ADDRESS_MASK)     /* Due to the 32-byte alignment of MPU-protected segments
                                                            * described in the ARM M33 documentation,
                                                            * all Start Addresses must be ANDed with this Mask */
 
#define MPU_END_ADDRESS_MASK (0x1F)                        /* Due to the 32-byte alignment of MPU-protected segments
                                                            * and the MPU region size must be a multiple of 32 bytes
                                                            * described in the ARM M33 documentation,
                                                            * all End Addresses must be ORed with this Mask */
 
typedef enum {
        HW_MPU_REGION_NONE = MPU_REGION_NONE,   
        HW_MPU_REGION_0 = MPU_REGION_0,         
        HW_MPU_REGION_1 = MPU_REGION_1,         
        HW_MPU_REGION_2 = MPU_REGION_2,         
        HW_MPU_REGION_3 = MPU_REGION_3,         
        HW_MPU_REGION_4 = MPU_REGION_4,         
        HW_MPU_REGION_5 = MPU_REGION_5,         
        HW_MPU_REGION_6 = MPU_REGION_6,         
        HW_MPU_REGION_7 = MPU_REGION_7,         
} HW_MPU_REGION_NUM;
typedef enum {
        HW_MPU_XN_FALSE = 0x00,         
        HW_MPU_XN_TRUE = 0x01,          
} HW_MPU_XN;
 
typedef enum {
        HW_MPU_APH_RO_RW = 0x00,         
        HW_MPU_APH_RO_RO = 0x01,         
} HW_MPU_APH_RO;
 
typedef enum {
        HW_MPU_APL_NP_PRIVRW = 0x00,     
        HW_MPU_APL_NP_RW = 0x01,         
} HW_MPU_APL_NP;
 
typedef enum {
        HW_MPU_AP_PRIVRW = ARM_MPU_AP_(HW_MPU_APH_RO_RW, HW_MPU_APL_NP_PRIVRW), 
        HW_MPU_AP_RW = ARM_MPU_AP_(HW_MPU_APH_RO_RW, HW_MPU_APL_NP_RW),         
        HW_MPU_AP_PRIVRO = ARM_MPU_AP_(HW_MPU_APH_RO_RO, HW_MPU_APL_NP_PRIVRW), 
        HW_MPU_AP_RO = ARM_MPU_AP_(HW_MPU_APH_RO_RO, HW_MPU_APL_NP_RW),         
} HW_MPU_AP;
 
typedef enum {
        HW_MPU_ATTR_INDEX_0,         
        HW_MPU_ATTR_INDEX_1,         
        HW_MPU_ATTR_INDEX_2,         
        HW_MPU_ATTR_INDEX_3,         
        HW_MPU_ATTR_INDEX_4,         
        HW_MPU_ATTR_INDEX_5,         
        HW_MPU_ATTR_INDEX_6,         
        HW_MPU_ATTR_INDEX_7          
} HW_MPU_ATTR_INDEX;
 
typedef enum {
        HW_MPU_SH_NS = ARM_MPU_SH_NON,          
        HW_MPU_SH_OS = ARM_MPU_SH_OUTER,        
        HW_MPU_SH_IS = ARM_MPU_SH_INNER,        
} HW_MPU_SH;
 
typedef enum {
        HW_MPU_ATTR_DEVICE = 0x00,      
        HW_MPU_ATTR_NORMAL = 0x44,      
} HW_MPU_ATTR;
 
typedef struct {
        uint32_t start_addr;            
        uint32_t end_addr;              
        HW_MPU_AP access_permissions;   
        HW_MPU_SH shareability;         
        HW_MPU_XN execute_never;        
        HW_MPU_ATTR attributes;         
} mpu_region_config;
 
__STATIC_FORCEINLINE void hw_mpu_hardfault_nmi_handlers_enable(bool hfnmiena)
{
        REG_SETF(MPU, CTRL, HFNMIENA, hfnmiena);
}
 
__STATIC_FORCEINLINE void hw_mpu_privileged_background_access_enable(bool privdefena)
{
        REG_SETF(MPU, CTRL, PRIVDEFENA, privdefena);
}
 
__STATIC_FORCEINLINE void hw_mpu_enable(bool privdefena)
{
        uint32_t MPU_Control = (privdefena ? REG_MSK(MPU, CTRL, PRIVDEFENA) : 0);
        ARM_MPU_Enable(MPU_Control);
}
 
__STATIC_FORCEINLINE void hw_mpu_disable(void)
{
        ARM_MPU_Disable();
        __ISB();
}
 
__STATIC_FORCEINLINE bool hw_mpu_is_enabled(void)
{
        return (!!REG_GETF(MPU, CTRL, ENABLE));
}
 
void hw_mpu_set_attribute_indirection(HW_MPU_REGION_NUM region_num, HW_MPU_ATTR_INDEX attr);
 
void hw_mpu_reset_attribute_indirections();
 
void hw_mpu_config_region(HW_MPU_REGION_NUM region_num, mpu_region_config *cfg);
 
void hw_mpu_fetch_region_configuration(HW_MPU_REGION_NUM region_num, mpu_region_config *cfg);
 
#endif /* dg_configUSE_HW_MPU */
 
 
#endif /* HW_MPU_H_ */