SmartSnippets DA1459x SDK
core_cm0.h
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1 /**************************************************************************/
8 /*
9  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
10  *
11  * SPDX-License-Identifier: Apache-2.0
12  *
13  * Licensed under the Apache License, Version 2.0 (the License); you may
14  * not use this file except in compliance with the License.
15  * You may obtain a copy of the License at
16  *
17  * www.apache.org/licenses/LICENSE-2.0
18  *
19  * Unless required by applicable law or agreed to in writing, software
20  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22  * See the License for the specific language governing permissions and
23  * limitations under the License.
24  */
25  /* Copyright (c) 2019-2023 Modified by Renesas Electronics Corporation and/or its affiliates. */
26 
27 #if defined ( __ICCARM__ )
28  #pragma system_include /* treat file as system include file for MISRA check */
29 #elif defined (__clang__)
30  #pragma clang system_header /* treat file as system include file */
31 #endif
32 
33 #ifndef __CORE_CM0_H_GENERIC
34 #define __CORE_CM0_H_GENERIC
35 
36 #include <stdint.h>
37 
38 #ifdef __cplusplus
39  extern "C" {
40 #endif
41 
58 /*******************************************************************************
59  * CMSIS definitions
60  ******************************************************************************/
66 #include "cmsis_version.h"
67 
68 /* CMSIS CM0 definitions */
69 #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
70 #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
71 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
72  __CM0_CMSIS_VERSION_SUB )
74 #define __CORTEX_M (0U)
79 #define __FPU_USED 0U
80 
81 #if defined ( __CC_ARM )
82  #if defined __TARGET_FPU_VFP
83  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84  #endif
85 
86 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
87  #if defined __ARM_FP
88  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
89  #endif
90 
91 #elif defined ( __GNUC__ )
92  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
93  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94  #endif
95 
96 #elif defined ( __ICCARM__ )
97  #if defined __ARMVFP__
98  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
99  #endif
100 
101 #elif defined ( __TI_ARM__ )
102  #if defined __TI_VFP_SUPPORT__
103  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
104  #endif
105 
106 #elif defined ( __TASKING__ )
107  #if defined __FPU_VFP__
108  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
109  #endif
110 
111 #elif defined ( __CSMC__ )
112  #if ( __CSMC__ & 0x400U)
113  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
114  #endif
115 
116 #endif
117 
118 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
119 
120 
121 #ifdef __cplusplus
122 }
123 #endif
124 
125 #endif /* __CORE_CM0_H_GENERIC */
126 
127 #ifndef __CMSIS_GENERIC
128 
129 #ifndef __CORE_CM0_H_DEPENDANT
130 #define __CORE_CM0_H_DEPENDANT
131 
132 #ifdef __cplusplus
133  extern "C" {
134 #endif
135 
136 /* check device defines and use defaults */
137 #if defined __CHECK_DEVICE_DEFINES
138  #ifndef __CM0_REV
139  #define __CM0_REV 0x0000U
140  #warning "__CM0_REV not defined in device header file; using default!"
141  #endif
142 
143  #ifndef __NVIC_PRIO_BITS
144  #define __NVIC_PRIO_BITS 2U
145  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
146  #endif
147 
148  #ifndef __Vendor_SysTickConfig
149  #define __Vendor_SysTickConfig 0U
150  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
151  #endif
152 #endif
153 
154 /* IO definitions (access restrictions to peripheral registers) */
163 #ifdef __cplusplus
164  #define __I volatile
165 #else
166  #define __I volatile const
167 #endif
168 #define __O volatile
169 #define __IO volatile
171 /* following defines should be used for structure members */
172 #define __IM volatile const
173 #define __OM volatile
174 #define __IOM volatile
179 /*******************************************************************************
180  * Register Abstraction
181  Core Register contain:
182  - Core Register
183  - Core NVIC Register
184  - Core SCB Register
185  - Core SysTick Register
186  ******************************************************************************/
187 
203 typedef union
204 {
205  struct
206  {
207  uint32_t _reserved0:28;
208  uint32_t V:1;
209  uint32_t C:1;
210  uint32_t Z:1;
211  uint32_t N:1;
212  } b;
213  uint32_t w;
214 } APSR_Type;
215 
216 /* APSR Register Definitions */
217 #define APSR_N_Pos 31U
218 #define APSR_N_Msk (1UL << APSR_N_Pos)
220 #define APSR_Z_Pos 30U
221 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
223 #define APSR_C_Pos 29U
224 #define APSR_C_Msk (1UL << APSR_C_Pos)
226 #define APSR_V_Pos 28U
227 #define APSR_V_Msk (1UL << APSR_V_Pos)
233 typedef union
234 {
235  struct
236  {
237  uint32_t ISR:9;
238  uint32_t _reserved0:23;
239  } b;
240  uint32_t w;
241 } IPSR_Type;
242 
243 /* IPSR Register Definitions */
244 #define IPSR_ISR_Pos 0U
245 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
251 typedef union
252 {
253  struct
254  {
255  uint32_t ISR:9;
256  uint32_t _reserved0:15;
257  uint32_t T:1;
258  uint32_t _reserved1:3;
259  uint32_t V:1;
260  uint32_t C:1;
261  uint32_t Z:1;
262  uint32_t N:1;
263  } b;
264  uint32_t w;
265 } xPSR_Type;
266 
267 /* xPSR Register Definitions */
268 #define xPSR_N_Pos 31U
269 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
271 #define xPSR_Z_Pos 30U
272 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
274 #define xPSR_C_Pos 29U
275 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
277 #define xPSR_V_Pos 28U
278 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
280 #define xPSR_T_Pos 24U
281 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
283 #define xPSR_ISR_Pos 0U
284 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
290 typedef union
291 {
292  struct
293  {
294  uint32_t _reserved0:1;
295  uint32_t SPSEL:1;
296  uint32_t _reserved1:30;
297  } b;
298  uint32_t w;
299 } CONTROL_Type;
300 
301 /* CONTROL Register Definitions */
302 #define CONTROL_SPSEL_Pos 1U
303 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
318 typedef struct
319 {
320  __IOM uint32_t ISER[1U];
321  uint32_t RESERVED0[31U];
322  __IOM uint32_t ICER[1U];
323  uint32_t RESERVED1[31U];
324  __IOM uint32_t ISPR[1U];
325  uint32_t RESERVED2[31U];
326  __IOM uint32_t ICPR[1U];
327  uint32_t RESERVED3[31U];
328  uint32_t RESERVED4[64U];
329  __IOM uint32_t IP[8U];
330 } NVIC_Type;
331 
345 typedef struct
346 {
347  __IM uint32_t CPUID;
348  __IOM uint32_t ICSR;
349  uint32_t RESERVED0;
350  __IOM uint32_t AIRCR;
351  __IOM uint32_t SCR;
352  __IOM uint32_t CCR;
353  uint32_t RESERVED1;
354  __IOM uint32_t SHP[2U];
355  __IOM uint32_t SHCSR;
356 } SCB_Type;
357 
358 /* SCB CPUID Register Definitions */
359 #define SCB_CPUID_IMPLEMENTER_Pos 24U
360 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
362 #define SCB_CPUID_VARIANT_Pos 20U
363 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
365 #define SCB_CPUID_ARCHITECTURE_Pos 16U
366 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
368 #define SCB_CPUID_PARTNO_Pos 4U
369 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
371 #define SCB_CPUID_REVISION_Pos 0U
372 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
374 /* SCB Interrupt Control State Register Definitions */
375 #define SCB_ICSR_NMIPENDSET_Pos 31U
376 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
378 #define SCB_ICSR_PENDSVSET_Pos 28U
379 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
381 #define SCB_ICSR_PENDSVCLR_Pos 27U
382 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
384 #define SCB_ICSR_PENDSTSET_Pos 26U
385 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
387 #define SCB_ICSR_PENDSTCLR_Pos 25U
388 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
390 #define SCB_ICSR_ISRPREEMPT_Pos 23U
391 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
393 #define SCB_ICSR_ISRPENDING_Pos 22U
394 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
396 #define SCB_ICSR_VECTPENDING_Pos 12U
397 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
399 #define SCB_ICSR_VECTACTIVE_Pos 0U
400 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
402 /* SCB Application Interrupt and Reset Control Register Definitions */
403 #define SCB_AIRCR_VECTKEY_Pos 16U
404 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
406 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
407 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
409 #define SCB_AIRCR_ENDIANESS_Pos 15U
410 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
412 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
413 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
415 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
416 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
418 /* SCB System Control Register Definitions */
419 #define SCB_SCR_SEVONPEND_Pos 4U
420 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
422 #define SCB_SCR_SLEEPDEEP_Pos 2U
423 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
425 #define SCB_SCR_SLEEPONEXIT_Pos 1U
426 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
428 /* SCB Configuration Control Register Definitions */
429 #define SCB_CCR_STKALIGN_Pos 9U
430 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
432 #define SCB_CCR_UNALIGN_TRP_Pos 3U
433 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
435 /* SCB System Handler Control and State Register Definitions */
436 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
437 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
452 typedef struct
453 {
454  __IOM uint32_t CTRL;
455  __IOM uint32_t LOAD;
456  __IOM uint32_t VAL;
457  __IM uint32_t CALIB;
458 } SysTick_Type;
459 
460 /* SysTick Control / Status Register Definitions */
461 #define SysTick_CTRL_COUNTFLAG_Pos 16U
462 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
464 #define SysTick_CTRL_CLKSOURCE_Pos 2U
465 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
467 #define SysTick_CTRL_TICKINT_Pos 1U
468 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
470 #define SysTick_CTRL_ENABLE_Pos 0U
471 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
473 /* SysTick Reload Register Definitions */
474 #define SysTick_LOAD_RELOAD_Pos 0U
475 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
477 /* SysTick Current Register Definitions */
478 #define SysTick_VAL_CURRENT_Pos 0U
479 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
481 /* SysTick Calibration Register Definitions */
482 #define SysTick_CALIB_NOREF_Pos 31U
483 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
485 #define SysTick_CALIB_SKEW_Pos 30U
486 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
488 #define SysTick_CALIB_TENMS_Pos 0U
489 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
517 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
518 
525 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
526 
537 /* Memory mapping of Core Hardware */
538 #define SCS_BASE (0xE000E000UL)
539 #define SysTick_BASE (SCS_BASE + 0x0010UL)
540 #define NVIC_BASE (SCS_BASE + 0x0100UL)
541 #define SCB_BASE (SCS_BASE + 0x0D00UL)
543 #define SCB ((SCB_Type *) SCB_BASE )
544 #define SysTick ((SysTick_Type *) SysTick_BASE )
545 #define NVIC ((NVIC_Type *) NVIC_BASE )
552 /*******************************************************************************
553  * Hardware Abstraction Layer
554  Core Function Interface contains:
555  - Core NVIC Functions
556  - Core SysTick Functions
557  - Core Register Access Functions
558  ******************************************************************************/
559 
565 /* ########################## NVIC functions #################################### */
573 #ifdef CMSIS_NVIC_VIRTUAL
574  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
575  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
576  #endif
577  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
578 #else
579  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
580  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
581  #define NVIC_EnableIRQ __NVIC_EnableIRQ
582  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
583  #define NVIC_DisableIRQ __NVIC_DisableIRQ
584  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
585  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
586  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
587 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
588  #define NVIC_SetPriority __NVIC_SetPriority
589  #define NVIC_GetPriority __NVIC_GetPriority
590  #define NVIC_SystemReset __NVIC_SystemReset
591 #endif /* CMSIS_NVIC_VIRTUAL */
592 
593 #ifdef CMSIS_VECTAB_VIRTUAL
594  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
595  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
596  #endif
597  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
598 #else
599  #define NVIC_SetVector __NVIC_SetVector
600  #define NVIC_GetVector __NVIC_GetVector
601 #endif /* (CMSIS_VECTAB_VIRTUAL) */
602 
603 #define NVIC_USER_IRQ_OFFSET 16
604 
605 
606 /* The following EXC_RETURN values are saved the LR on exception entry */
607 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
608 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
609 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
610 
611 
612 /* Interrupt Priorities are WORD accessible only under Armv6-M */
613 /* The following MACROS handle generation of the register offset and byte masks */
614 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
615 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
616 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
617 
618 #define __NVIC_SetPriorityGrouping(X) (void)(X)
619 #define __NVIC_GetPriorityGrouping() (0U)
620 
627 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
628 {
629  if ((int32_t)(IRQn) >= 0)
630  {
631  __COMPILER_BARRIER();
632  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
633  __COMPILER_BARRIER();
634  }
635 }
636 
637 
646 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
647 {
648  if ((int32_t)(IRQn) >= 0)
649  {
650  return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
651  }
652  else
653  {
654  return(0U);
655  }
656 }
657 
658 
665 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
666 {
667  if ((int32_t)(IRQn) >= 0)
668  {
669  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
670  __DSB();
671  __ISB();
672  }
673 }
674 
675 
684 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
685 {
686  if ((int32_t)(IRQn) >= 0)
687  {
688  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
689  }
690  else
691  {
692  return(0U);
693  }
694 }
695 
696 
703 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
704 {
705  if ((int32_t)(IRQn) >= 0)
706  {
707  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
708  }
709 }
710 
711 
718 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
719 {
720  if ((int32_t)(IRQn) >= 0)
721  {
722  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
723  }
724 }
725 
726 
736 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
737 {
738  if ((int32_t)(IRQn) >= 0)
739  {
740  NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
741  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
742  }
743  else
744  {
745  SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
746  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
747  }
748 }
749 
750 
760 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
761 {
762 
763  if ((int32_t)(IRQn) >= 0)
764  {
765  return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
766  }
767  else
768  {
769  return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
770  }
771 }
772 
773 
785 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
786 {
787  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
788  uint32_t PreemptPriorityBits;
789  uint32_t SubPriorityBits;
790 
791  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
792  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
793 
794  return (
795  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
796  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
797  );
798 }
799 
800 
812 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
813 {
814  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
815  uint32_t PreemptPriorityBits;
816  uint32_t SubPriorityBits;
817 
818  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
819  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
820 
821  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
822  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
823 }
824 
825 
826 
836 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
837 {
838  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
839  *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
840  /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
841 }
842 
843 
852 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
853 {
854  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
855  return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
856 }
857 
858 
863 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
864 {
865  __DSB(); /* Ensure all outstanding memory accesses included
866  buffered write are completed before reset */
867  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
868  SCB_AIRCR_SYSRESETREQ_Msk);
869  __DSB(); /* Ensure completion of memory access */
870 
871  for(;;) /* wait until reset */
872  {
873  __NOP();
874  }
875 }
876 
880 /* ########################## FPU functions #################################### */
896 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
897 {
898  return 0U; /* No FPU */
899 }
900 
901 
906 /* ################################## SysTick function ############################################ */
914 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
915 
927 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
928 {
929  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
930  {
931  return (1UL); /* Reload value impossible */
932  }
933 
934  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
935  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
936  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
937  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
938  SysTick_CTRL_TICKINT_Msk |
939  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
940  return (0UL); /* Function successful */
941 }
942 
943 #endif
944 
949 #ifdef __cplusplus
950 }
951 #endif
952 
953 #endif /* __CORE_CM0_H_DEPENDANT */
954 
955 #endif /* __CMSIS_GENERIC */
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:451
__IOM
#define __IOM
Definition: core_cm0.h:174
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm0.h:402
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm0.h:412
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:250
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm0.h:470
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:874
NVIC
#define NVIC
Definition: core_cm0.h:544
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm0.h:783
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:701
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:344
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm0.h:474
IRQn_Type
IRQn_Type
Interrupt Number Definition.
Definition: DA1459x-00.h:67
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_cm0.h:625
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:885
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:716
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_cm0.h:834
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:232
cmsis_version.h
CMSIS Core(M) Version definitions.
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:734
SCB
#define SCB
Definition: core_cm0.h:542
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:682
__NOP
#define __NOP()
No Operation.
Definition: cmsis_gcc.h:844
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:289
SysTick
#define SysTick
Definition: core_cm0.h:543
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:758
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: DA1459x-00.h:129
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:317
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:861
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_cm0.h:810
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm0.h:467
__IM
#define __IM
Definition: core_cm0.h:172
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:202
cmsis_compiler.h
CMSIS compiler generic header file.
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_cm0.h:894
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_cm0.h:644
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_cm0.h:663
SysTick_IRQn
Definition: DA1459x-00.h:81
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm0.h:464
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_cm0.h:850
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