Memory Controller

Memory Controller. More...

Files
file	hw_memctrl.h
	Definition of API for the Memory Controller Low Level Driver.

Enumerations
enum	MEMCTRL_PRIO
	Priority values for SYSCPU, DMA and CMAC.

Functions
void	hw_memctrl_reset (void)
	Resets memory controller's configuration. More...
void	hw_memctrl_config_cmac_region (uint32_t code_base_addr, uint32_t data_base_addr, uint32_t shared_base_addr, uint32_t end_addr)
	Configures CMAC code, data and shared regions. More...
void	hw_memctrl_config_master_priorities (MEMCTRL_PRIO syscpu_prio, uint8_t syscpu_max_stall_cycles, MEMCTRL_PRIO dma_prio, uint8_t dma_max_stall_cycles)
	Configures RAM access priority for SYSCPU and DMA. More...

Detailed Description

Memory Controller.

Function Documentation

hw_memctrl_config_cmac_region()

void hw_memctrl_config_cmac_region	(	uint32_t	code_base_addr,
		uint32_t	data_base_addr,
		uint32_t	shared_base_addr,
		uint32_t	end_addr
	)

Configures CMAC code, data and shared regions.

Parameters

[in]	code_base_addr	CMAC code address. CMAC 0x00000000 address is remaped to this value. Must be multiple of 1024. The region [code_base_addr, shared_base_addr] is not accessible by DMA.
[in]	data_base_addr	CMAC data address. CMAC 0x20000000 address is remaped to this value. Must be multiple of 4.
[in]	shared_base_addr	CMAC code address. Must be multiple of 1024.
[in]	end_addr	The upper bound of RAM region that CMAC can access. Must end at 1024 byte boundary (10 last bits 0x3FF). DMA can only access the RAM region between shared_base_addr and end_addr addresses.

hw_memctrl_config_master_priorities()

void hw_memctrl_config_master_priorities	(	MEMCTRL_PRIO	syscpu_prio,
		uint8_t	syscpu_max_stall_cycles,
		MEMCTRL_PRIO	dma_prio,
		uint8_t	dma_max_stall_cycles
	)

Configures RAM access priority for SYSCPU and DMA.

CMAC and MTB have always priority over SYSCPU and DMA and they cannot operate on the same RAM cell (Since MTB is located at the last RAM cell CMAC should not operate there).

When SYSCPU or DMA request access on the same RAM cell (and CMAC or MTB do not), the PRIO fields determine which master will gain access. For the masters that did not get priority there is an internal counter (with initial value equal to the STALL cycles fields) that decreases by one. When the counter reaches zero, the specific master will gain access regardless of its PRIO for a single cycle and the internal counter will be reset again to the initial STALL value. This is done to avoid starvation of low priority masters.

A possible mapping of priorities to priority/stall cycle pair values could be the following:

• HIGHEST: PRIO 2, STALL 3
• HIGH: PRIO 2, STALL 6
• MEDIUM: PRIO 1, STALL 9
• LOW: PRIO 0, STALL 12
• LOWEST: PRIO 0, STALL 15

Configuring two masters with the same stall cycle values should be avoided, since the field was added to differentiate between masters.

Parameters

[in]	syscpu_prio	SYCPU priority
[in]	syscpu_max_stall_cycles	SYCPU max stall cycles (1 - 15)
[in]	dma_prio	DMA priority
[in]	dma_max_stall_cycles	DMA max stall cycles (1 - 15)

hw_memctrl_reset()

void hw_memctrl_reset

(

void

)

Resets memory controller's configuration.

Must be used only when CMAC master is disabled.