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SmartSnippets DA1459x SDK
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Type definitions for the System Control Block Registers. More...
Data Structures | |
| struct | SCB_Type |
| Structure type to access the System Control Block (SCB). More... | |
Type definitions for the System Control Block Registers.
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
| #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
SCB NSACR: CPn Mask
| #define SCB_NSACR_CPn_Pos 0U |
SCB NSACR: CPn Position
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
1.8.16