SmartSnippets DA1459x SDK
cmsis_gcc.h
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1 /**************************************************************************/
8 /*
9  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
10  *
11  * SPDX-License-Identifier: Apache-2.0
12  *
13  * Licensed under the Apache License, Version 2.0 (the License); you may
14  * not use this file except in compliance with the License.
15  * You may obtain a copy of the License at
16  *
17  * www.apache.org/licenses/LICENSE-2.0
18  *
19  * Unless required by applicable law or agreed to in writing, software
20  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22  * See the License for the specific language governing permissions and
23  * limitations under the License.
24  */
25  /* Copyright (c) 2019-2023 Modified by Renesas Electronics Corporation and/or its affiliates. */
26 
27 #ifndef __CMSIS_GCC_H
28 #define __CMSIS_GCC_H
29 
30 /* ignore some GCC warnings */
31 #pragma GCC diagnostic push
32 #pragma GCC diagnostic ignored "-Wsign-conversion"
33 #pragma GCC diagnostic ignored "-Wconversion"
34 #pragma GCC diagnostic ignored "-Wunused-parameter"
35 
36 /* Fallback for __has_builtin */
37 #ifndef __has_builtin
38  #define __has_builtin(x) (0)
39 #endif
40 
41 /* CMSIS compiler specific defines */
42 #ifndef __ASM
43  #define __ASM __asm
44 #endif
45 #ifndef __INLINE
46  #define __INLINE inline
47 #endif
48 #ifndef __STATIC_INLINE
49  #define __STATIC_INLINE static inline
50 #endif
51 #ifndef __STATIC_FORCEINLINE
52  #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
53 #endif
54 #ifndef __NO_RETURN
55  #define __NO_RETURN __attribute__((__noreturn__))
56 #endif
57 #ifndef __USED
58  #define __USED __attribute__((used))
59 #endif
60 #ifndef __WEAK
61  #define __WEAK __attribute__((weak))
62 #endif
63 #ifndef __PACKED
64  #define __PACKED __attribute__((packed, aligned(1)))
65 #endif
66 #ifndef __PACKED_STRUCT
67  #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
68 #endif
69 #ifndef __PACKED_UNION
70  #define __PACKED_UNION union __attribute__((packed, aligned(1)))
71 #endif
72 #ifndef __UNALIGNED_UINT32 /* deprecated */
73  #pragma GCC diagnostic push
74  #pragma GCC diagnostic ignored "-Wpacked"
75  #pragma GCC diagnostic ignored "-Wattributes"
76  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
77  #pragma GCC diagnostic pop
78  #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
79 #endif
80 #ifndef __UNALIGNED_UINT16_WRITE
81  #pragma GCC diagnostic push
82  #pragma GCC diagnostic ignored "-Wpacked"
83  #pragma GCC diagnostic ignored "-Wattributes"
84  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
85  #pragma GCC diagnostic pop
86  #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
87 #endif
88 #ifndef __UNALIGNED_UINT16_READ
89  #pragma GCC diagnostic push
90  #pragma GCC diagnostic ignored "-Wpacked"
91  #pragma GCC diagnostic ignored "-Wattributes"
92  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
93  #pragma GCC diagnostic pop
94  #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
95 #endif
96 #ifndef __UNALIGNED_UINT32_WRITE
97  #pragma GCC diagnostic push
98  #pragma GCC diagnostic ignored "-Wpacked"
99  #pragma GCC diagnostic ignored "-Wattributes"
100  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
101  #pragma GCC diagnostic pop
102  #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
103 #endif
104 #ifndef __UNALIGNED_UINT32_READ
105  #pragma GCC diagnostic push
106  #pragma GCC diagnostic ignored "-Wpacked"
107  #pragma GCC diagnostic ignored "-Wattributes"
108  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
109  #pragma GCC diagnostic pop
110  #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
111 #endif
112 #ifndef __ALIGNED
113  #define __ALIGNED(x) __attribute__((aligned(x)))
114 #endif
115 #ifndef __RESTRICT
116  #define __RESTRICT __restrict
117 #endif
118 #ifndef __COMPILER_BARRIER
119  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
120 #endif
121 
122  __STATIC_FORCEINLINE void __ISB(void);
123 
124 /* ########################### Core Function Access ########################### */
135 __STATIC_FORCEINLINE void __enable_irq(void)
136 {
137  __ASM volatile ("cpsie i" : : : "memory");
138 }
139 
140 
146 __STATIC_FORCEINLINE void __disable_irq(void)
147 {
148  __ASM volatile ("cpsid i" : : : "memory");
149 }
150 
151 
157 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
158 {
159  uint32_t result;
160 
161  __ASM volatile ("MRS %0, control" : "=r" (result) );
162  return(result);
163 }
164 
165 
166 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
167 
172 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
173 {
174  uint32_t result;
175 
176  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
177  return(result);
178 }
179 #endif
180 
181 
187 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
188 {
189  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
190  __ISB();
191 }
192 
193 
194 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
195 
200 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
201 {
202  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
203  __ISB();
204 }
205 #endif
206 
207 
213 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
214 {
215  uint32_t result;
216 
217  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
218  return(result);
219 }
220 
221 
227 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
228 {
229  uint32_t result;
230 
231  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
232  return(result);
233 }
234 
235 
241 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
242 {
243  uint32_t result;
244 
245  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
246  return(result);
247 }
248 
249 
255 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
256 {
257  uint32_t result;
258 
259  __ASM volatile ("MRS %0, psp" : "=r" (result) );
260  return(result);
261 }
262 
263 
264 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
265 
270 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
271 {
272  uint32_t result;
273 
274  __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
275  return(result);
276 }
277 #endif
278 
279 
285 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
286 {
287  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
288 }
289 
290 
291 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
292 
297 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
298 {
299  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
300 }
301 #endif
302 
303 
309 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
310 {
311  uint32_t result;
312 
313  __ASM volatile ("MRS %0, msp" : "=r" (result) );
314  return(result);
315 }
316 
317 
318 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
319 
324 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
325 {
326  uint32_t result;
327 
328  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
329  return(result);
330 }
331 #endif
332 
333 
339 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
340 {
341  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
342 }
343 
344 
345 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
346 
351 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
352 {
353  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
354 }
355 #endif
356 
357 
358 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
359 
364 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
365 {
366  uint32_t result;
367 
368  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
369  return(result);
370 }
371 
372 
378 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
379 {
380  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
381 }
382 #endif
383 
384 
390 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
391 {
392  uint32_t result;
393 
394  __ASM volatile ("MRS %0, primask" : "=r" (result) );
395  return(result);
396 }
397 
398 
399 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
400 
405 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
406 {
407  uint32_t result;
408 
409  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
410  return(result);
411 }
412 #endif
413 
414 
420 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
421 {
422  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
423 }
424 
425 
426 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
427 
432 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
433 {
434  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
435 }
436 #endif
437 
438 
439 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
440  (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
441  (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
442 
447 __STATIC_FORCEINLINE void __enable_fault_irq(void)
448 {
449  __ASM volatile ("cpsie f" : : : "memory");
450 }
451 
452 
458 __STATIC_FORCEINLINE void __disable_fault_irq(void)
459 {
460  __ASM volatile ("cpsid f" : : : "memory");
461 }
462 
463 
469 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
470 {
471  uint32_t result;
472 
473  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
474  return(result);
475 }
476 
477 
478 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
479 
484 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
485 {
486  uint32_t result;
487 
488  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
489  return(result);
490 }
491 #endif
492 
493 
499 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
500 {
501  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
502 }
503 
504 
505 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
506 
511 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
512 {
513  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
514 }
515 #endif
516 
517 
524 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
525 {
526  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
527 }
528 
529 
535 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
536 {
537  uint32_t result;
538 
539  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
540  return(result);
541 }
542 
543 
544 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
545 
550 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
551 {
552  uint32_t result;
553 
554  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
555  return(result);
556 }
557 #endif
558 
559 
565 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
566 {
567  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
568 }
569 
570 
571 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
572 
577 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
578 {
579  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
580 }
581 #endif
582 
583 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
584  (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
585  (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
586 
587 
588 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
589  (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
590 
600 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
601 {
602 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
603  (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
604  // without main extensions, the non-secure PSPLIM is RAZ/WI
605  return 0U;
606 #else
607  uint32_t result;
608  __ASM volatile ("MRS %0, psplim" : "=r" (result) );
609  return result;
610 #endif
611 }
612 
613 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
614 
622 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
623 {
624 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
625  // without main extensions, the non-secure PSPLIM is RAZ/WI
626  return 0U;
627 #else
628  uint32_t result;
629  __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
630  return result;
631 #endif
632 }
633 #endif
634 
635 
645 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
646 {
647 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
648  (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
649  // without main extensions, the non-secure PSPLIM is RAZ/WI
650  (void)ProcStackPtrLimit;
651 #else
652  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
653 #endif
654 }
655 
656 
657 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
658 
666 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
667 {
668 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
669  // without main extensions, the non-secure PSPLIM is RAZ/WI
670  (void)ProcStackPtrLimit;
671 #else
672  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
673 #endif
674 }
675 #endif
676 
677 
687 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
688 {
689 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
690  (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
691  // without main extensions, the non-secure MSPLIM is RAZ/WI
692  return 0U;
693 #else
694  uint32_t result;
695  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
696  return result;
697 #endif
698 }
699 
700 
701 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
702 
710 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
711 {
712 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
713  // without main extensions, the non-secure MSPLIM is RAZ/WI
714  return 0U;
715 #else
716  uint32_t result;
717  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
718  return result;
719 #endif
720 }
721 #endif
722 
723 
733 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
734 {
735 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
736  (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
737  // without main extensions, the non-secure MSPLIM is RAZ/WI
738  (void)MainStackPtrLimit;
739 #else
740  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
741 #endif
742 }
743 
744 
745 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
746 
754 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
755 {
756 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
757  // without main extensions, the non-secure MSPLIM is RAZ/WI
758  (void)MainStackPtrLimit;
759 #else
760  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
761 #endif
762 }
763 #endif
764 
765 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
766  (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
767 
768 
774 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
775 {
776 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
777  (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
778 #if __has_builtin(__builtin_arm_get_fpscr)
779 // Re-enable using built-in when GCC has been fixed
780 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
781  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
782  return __builtin_arm_get_fpscr();
783 #else
784  uint32_t result;
785 
786  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
787  return(result);
788 #endif
789 #else
790  return(0U);
791 #endif
792 }
793 
794 
800 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
801 {
802 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
803  (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
804 #if __has_builtin(__builtin_arm_set_fpscr)
805 // Re-enable using built-in when GCC has been fixed
806 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
807  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
808  __builtin_arm_set_fpscr(fpscr);
809 #else
810  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
811 #endif
812 #else
813  (void)fpscr;
814 #endif
815 }
816 
817 
821 /* ########################## Core Instruction Access ######################### */
827 /* Define macros for porting to both thumb1 and thumb2.
828  * For thumb1, use low register (r0-r7), specified by constraint "l"
829  * Otherwise, use general registers, specified by constraint "r" */
830 #if defined (__thumb__) && !defined (__thumb2__)
831 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
832 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
833 #define __CMSIS_GCC_USE_REG(r) "l" (r)
834 #else
835 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
836 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
837 #define __CMSIS_GCC_USE_REG(r) "r" (r)
838 #endif
839 
844 #define __NOP() __ASM volatile ("nop")
845 
850 #define __WFI() __ASM volatile ("wfi":::"memory")
851 
852 
858 #define __WFE() __ASM volatile ("wfe":::"memory")
859 
860 
865 #define __SEV() __ASM volatile ("sev")
866 
867 
874 __STATIC_FORCEINLINE void __ISB(void)
875 {
876  __ASM volatile ("isb 0xF":::"memory");
877 }
878 
879 
885 __STATIC_FORCEINLINE void __DSB(void)
886 {
887  __ASM volatile ("dsb 0xF":::"memory");
888 }
889 
890 
896 __STATIC_FORCEINLINE void __DMB(void)
897 {
898  __ASM volatile ("dmb 0xF":::"memory");
899 }
900 
901 
908 __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
909 {
910 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
911  return __builtin_bswap32(value);
912 #else
913  uint32_t result;
914 
915  __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
916  return result;
917 #endif
918 }
919 
920 
927 __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
928 {
929  uint32_t result;
930 
931  __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
932  return result;
933 }
934 
935 
942 __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
943 {
944 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
945  return (int16_t)__builtin_bswap16(value);
946 #else
947  int16_t result;
948 
949  __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
950  return result;
951 #endif
952 }
953 
954 
962 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
963 {
964  op2 %= 32U;
965  if (op2 == 0U)
966  {
967  return op1;
968  }
969  return (op1 >> op2) | (op1 << (32U - op2));
970 }
971 
972 
980 #define __BKPT(value) __ASM volatile ("bkpt "#value)
981 
982 
989 __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
990 {
991  uint32_t result;
992 
993 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
994  (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
995  (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
996  __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
997 #else
998  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
999 
1000  result = value; /* r will be reversed bits of v; first get LSB of v */
1001  for (value >>= 1U; value != 0U; value >>= 1U)
1002  {
1003  result <<= 1U;
1004  result |= value & 1U;
1005  s--;
1006  }
1007  result <<= s; /* shift when v's highest bits are zero */
1008 #endif
1009  return result;
1010 }
1011 
1012 
1019 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
1020 {
1021  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
1022  __builtin_clz(0) is undefined behaviour, so handle this case specially.
1023  This guarantees ARM-compatible results if happening to compile on a non-ARM
1024  target, and ensures the compiler doesn't decide to activate any
1025  optimisations using the logic "value was passed to __builtin_clz, so it
1026  is non-zero".
1027  ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
1028  single CLZ instruction.
1029  */
1030  if (value == 0U)
1031  {
1032  return 32U;
1033  }
1034  return __builtin_clz(value);
1035 }
1036 
1037 
1038 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1039  (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1040  (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1041  (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
1042 
1048 __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
1049 {
1050  uint32_t result;
1051 
1052 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1053  __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
1054 #else
1055  /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
1056  accepted by assembler. So has to use following less efficient pattern.
1057  */
1058  __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
1059 #endif
1060  return ((uint8_t) result); /* Add explicit type cast here */
1061 }
1062 
1063 
1070 __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
1071 {
1072  uint32_t result;
1073 
1074 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1075  __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
1076 #else
1077  /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
1078  accepted by assembler. So has to use following less efficient pattern.
1079  */
1080  __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
1081 #endif
1082  return ((uint16_t) result); /* Add explicit type cast here */
1083 }
1084 
1085 
1092 __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
1093 {
1094  uint32_t result;
1095 
1096  __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
1097  return(result);
1098 }
1099 
1100 
1109 __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
1110 {
1111  uint32_t result;
1112 
1113  __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
1114  return(result);
1115 }
1116 
1117 
1126 __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
1127 {
1128  uint32_t result;
1129 
1130  __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
1131  return(result);
1132 }
1133 
1134 
1143 __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
1144 {
1145  uint32_t result;
1146 
1147  __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
1148  return(result);
1149 }
1150 
1151 
1156 __STATIC_FORCEINLINE void __CLREX(void)
1157 {
1158  __ASM volatile ("clrex" ::: "memory");
1159 }
1160 
1161 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1162  (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1163  (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1164  (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1165 
1166 
1167 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1168  (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1169  (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
1170 
1177 #define __SSAT(ARG1,ARG2) \
1178 __extension__ \
1179 ({ \
1180  int32_t __RES, __ARG1 = (ARG1); \
1181  __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
1182  __RES; \
1183  })
1184 
1185 
1193 #define __USAT(ARG1,ARG2) \
1194 __extension__ \
1195 ({ \
1196  uint32_t __RES, __ARG1 = (ARG1); \
1197  __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
1198  __RES; \
1199  })
1200 
1201 
1209 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
1210 {
1211  uint32_t result;
1212 
1213  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
1214  return(result);
1215 }
1216 
1217 
1224 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
1225 {
1226  uint32_t result;
1227 
1228 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1229  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
1230 #else
1231  /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
1232  accepted by assembler. So has to use following less efficient pattern.
1233  */
1234  __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
1235 #endif
1236  return ((uint8_t) result); /* Add explicit type cast here */
1237 }
1238 
1239 
1246 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
1247 {
1248  uint32_t result;
1249 
1250 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1251  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
1252 #else
1253  /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
1254  accepted by assembler. So has to use following less efficient pattern.
1255  */
1256  __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
1257 #endif
1258  return ((uint16_t) result); /* Add explicit type cast here */
1259 }
1260 
1261 
1268 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
1269 {
1270  uint32_t result;
1271 
1272  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
1273  return(result);
1274 }
1275 
1276 
1283 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
1284 {
1285  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1286 }
1287 
1288 
1295 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
1296 {
1297  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1298 }
1299 
1300 
1307 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
1308 {
1309  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
1310 }
1311 
1312 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1313  (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1314  (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1315 
1323 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
1324 {
1325  if ((sat >= 1U) && (sat <= 32U))
1326  {
1327  const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
1328  const int32_t min = -1 - max ;
1329  if (val > max)
1330  {
1331  return max;
1332  }
1333  else if (val < min)
1334  {
1335  return min;
1336  }
1337  }
1338  return val;
1339 }
1340 
1348 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
1349 {
1350  if (sat <= 31U)
1351  {
1352  const uint32_t max = ((1U << sat) - 1U);
1353  if (val > (int32_t)max)
1354  {
1355  return max;
1356  }
1357  else if (val < 0)
1358  {
1359  return 0U;
1360  }
1361  }
1362  return (uint32_t)val;
1363 }
1364 
1365 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1366  (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1367  (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1368 
1369 
1370 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1371  (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
1372 
1378 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
1379 {
1380  uint32_t result;
1381 
1382  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
1383  return ((uint8_t) result);
1384 }
1385 
1386 
1393 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
1394 {
1395  uint32_t result;
1396 
1397  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
1398  return ((uint16_t) result);
1399 }
1400 
1401 
1408 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
1409 {
1410  uint32_t result;
1411 
1412  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
1413  return(result);
1414 }
1415 
1416 
1423 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
1424 {
1425  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
1426 }
1427 
1428 
1435 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
1436 {
1437  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
1438 }
1439 
1440 
1447 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
1448 {
1449  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
1450 }
1451 
1452 
1459 __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
1460 {
1461  uint32_t result;
1462 
1463  __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
1464  return ((uint8_t) result);
1465 }
1466 
1467 
1474 __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
1475 {
1476  uint32_t result;
1477 
1478  __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
1479  return ((uint16_t) result);
1480 }
1481 
1482 
1489 __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
1490 {
1491  uint32_t result;
1492 
1493  __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
1494  return(result);
1495 }
1496 
1497 
1506 __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
1507 {
1508  uint32_t result;
1509 
1510  __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
1511  return(result);
1512 }
1513 
1514 
1523 __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
1524 {
1525  uint32_t result;
1526 
1527  __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
1528  return(result);
1529 }
1530 
1531 
1540 __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
1541 {
1542  uint32_t result;
1543 
1544  __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
1545  return(result);
1546 }
1547 
1548 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1549  (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1550  /* end of group CMSIS_Core_InstructionInterface */
1552 
1553 
1554 /* ################### Compiler specific Intrinsics ########################### */
1560 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1561 
1562 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
1563 {
1564  uint32_t result;
1565 
1566  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1567  return(result);
1568 }
1569 
1570 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
1571 {
1572  uint32_t result;
1573 
1574  __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1575  return(result);
1576 }
1577 
1578 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
1579 {
1580  uint32_t result;
1581 
1582  __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1583  return(result);
1584 }
1585 
1586 __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
1587 {
1588  uint32_t result;
1589 
1590  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1591  return(result);
1592 }
1593 
1594 __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
1595 {
1596  uint32_t result;
1597 
1598  __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1599  return(result);
1600 }
1601 
1602 __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
1603 {
1604  uint32_t result;
1605 
1606  __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1607  return(result);
1608 }
1609 
1610 
1611 __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
1612 {
1613  uint32_t result;
1614 
1615  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1616  return(result);
1617 }
1618 
1619 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
1620 {
1621  uint32_t result;
1622 
1623  __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1624  return(result);
1625 }
1626 
1627 __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
1628 {
1629  uint32_t result;
1630 
1631  __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1632  return(result);
1633 }
1634 
1635 __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
1636 {
1637  uint32_t result;
1638 
1639  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1640  return(result);
1641 }
1642 
1643 __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
1644 {
1645  uint32_t result;
1646 
1647  __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1648  return(result);
1649 }
1650 
1651 __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
1652 {
1653  uint32_t result;
1654 
1655  __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1656  return(result);
1657 }
1658 
1659 
1660 __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
1661 {
1662  uint32_t result;
1663 
1664  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1665  return(result);
1666 }
1667 
1668 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
1669 {
1670  uint32_t result;
1671 
1672  __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1673  return(result);
1674 }
1675 
1676 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
1677 {
1678  uint32_t result;
1679 
1680  __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1681  return(result);
1682 }
1683 
1684 __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
1685 {
1686  uint32_t result;
1687 
1688  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1689  return(result);
1690 }
1691 
1692 __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
1693 {
1694  uint32_t result;
1695 
1696  __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1697  return(result);
1698 }
1699 
1700 __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
1701 {
1702  uint32_t result;
1703 
1704  __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1705  return(result);
1706 }
1707 
1708 __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
1709 {
1710  uint32_t result;
1711 
1712  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1713  return(result);
1714 }
1715 
1716 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
1717 {
1718  uint32_t result;
1719 
1720  __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1721  return(result);
1722 }
1723 
1724 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
1725 {
1726  uint32_t result;
1727 
1728  __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1729  return(result);
1730 }
1731 
1732 __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
1733 {
1734  uint32_t result;
1735 
1736  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1737  return(result);
1738 }
1739 
1740 __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
1741 {
1742  uint32_t result;
1743 
1744  __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1745  return(result);
1746 }
1747 
1748 __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
1749 {
1750  uint32_t result;
1751 
1752  __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1753  return(result);
1754 }
1755 
1756 __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
1757 {
1758  uint32_t result;
1759 
1760  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1761  return(result);
1762 }
1763 
1764 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
1765 {
1766  uint32_t result;
1767 
1768  __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1769  return(result);
1770 }
1771 
1772 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
1773 {
1774  uint32_t result;
1775 
1776  __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1777  return(result);
1778 }
1779 
1780 __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
1781 {
1782  uint32_t result;
1783 
1784  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1785  return(result);
1786 }
1787 
1788 __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
1789 {
1790  uint32_t result;
1791 
1792  __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1793  return(result);
1794 }
1795 
1796 __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
1797 {
1798  uint32_t result;
1799 
1800  __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1801  return(result);
1802 }
1803 
1804 __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
1805 {
1806  uint32_t result;
1807 
1808  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1809  return(result);
1810 }
1811 
1812 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
1813 {
1814  uint32_t result;
1815 
1816  __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1817  return(result);
1818 }
1819 
1820 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
1821 {
1822  uint32_t result;
1823 
1824  __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1825  return(result);
1826 }
1827 
1828 __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
1829 {
1830  uint32_t result;
1831 
1832  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1833  return(result);
1834 }
1835 
1836 __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
1837 {
1838  uint32_t result;
1839 
1840  __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1841  return(result);
1842 }
1843 
1844 __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
1845 {
1846  uint32_t result;
1847 
1848  __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1849  return(result);
1850 }
1851 
1852 __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
1853 {
1854  uint32_t result;
1855 
1856  __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1857  return(result);
1858 }
1859 
1860 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
1861 {
1862  uint32_t result;
1863 
1864  __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1865  return(result);
1866 }
1867 
1868 #define __SSAT16(ARG1,ARG2) \
1869 __extension__ \
1870 ({ \
1871  int32_t __RES, __ARG1 = (ARG1); \
1872  __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
1873  __RES; \
1874  })
1875 
1876 #define __USAT16(ARG1,ARG2) \
1877 __extension__ \
1878 ({ \
1879  uint32_t __RES, __ARG1 = (ARG1); \
1880  __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
1881  __RES; \
1882  })
1883 
1884 __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
1885 {
1886  uint32_t result;
1887 
1888  __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
1889  return(result);
1890 }
1891 
1892 __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
1893 {
1894  uint32_t result;
1895 
1896  __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1897  return(result);
1898 }
1899 
1900 __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
1901 {
1902  uint32_t result;
1903 
1904  __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
1905  return(result);
1906 }
1907 
1908 __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
1909 {
1910  uint32_t result;
1911  if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
1912  __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
1913  } else {
1914  result = __SXTB16(__ROR(op1, rotate)) ;
1915  }
1916  return result;
1917 }
1918 
1919 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
1920 {
1921  uint32_t result;
1922 
1923  __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1924  return(result);
1925 }
1926 
1927 __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
1928 {
1929  uint32_t result;
1930  if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
1931  __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
1932  } else {
1933  result = __SXTAB16(op1, __ROR(op2, rotate));
1934  }
1935  return result;
1936 }
1937 
1938 __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
1939 {
1940  uint32_t result;
1941 
1942  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1943  return(result);
1944 }
1945 
1946 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
1947 {
1948  uint32_t result;
1949 
1950  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1951  return(result);
1952 }
1953 
1954 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
1955 {
1956  uint32_t result;
1957 
1958  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1959  return(result);
1960 }
1961 
1962 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
1963 {
1964  uint32_t result;
1965 
1966  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1967  return(result);
1968 }
1969 
1970 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
1971 {
1972  union llreg_u{
1973  uint32_t w32[2];
1974  uint64_t w64;
1975  } llr;
1976  llr.w64 = acc;
1977 
1978 #ifndef __ARMEB__ /* Little endian */
1979  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1980 #else /* Big endian */
1981  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1982 #endif
1983 
1984  return(llr.w64);
1985 }
1986 
1987 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
1988 {
1989  union llreg_u{
1990  uint32_t w32[2];
1991  uint64_t w64;
1992  } llr;
1993  llr.w64 = acc;
1994 
1995 #ifndef __ARMEB__ /* Little endian */
1996  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1997 #else /* Big endian */
1998  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1999 #endif
2000 
2001  return(llr.w64);
2002 }
2003 
2004 __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
2005 {
2006  uint32_t result;
2007 
2008  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2009  return(result);
2010 }
2011 
2012 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
2013 {
2014  uint32_t result;
2015 
2016  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2017  return(result);
2018 }
2019 
2020 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
2021 {
2022  uint32_t result;
2023 
2024  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
2025  return(result);
2026 }
2027 
2028 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
2029 {
2030  uint32_t result;
2031 
2032  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
2033  return(result);
2034 }
2035 
2036 __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
2037 {
2038  union llreg_u{
2039  uint32_t w32[2];
2040  uint64_t w64;
2041  } llr;
2042  llr.w64 = acc;
2043 
2044 #ifndef __ARMEB__ /* Little endian */
2045  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
2046 #else /* Big endian */
2047  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
2048 #endif
2049 
2050  return(llr.w64);
2051 }
2052 
2053 __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
2054 {
2055  union llreg_u{
2056  uint32_t w32[2];
2057  uint64_t w64;
2058  } llr;
2059  llr.w64 = acc;
2060 
2061 #ifndef __ARMEB__ /* Little endian */
2062  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
2063 #else /* Big endian */
2064  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
2065 #endif
2066 
2067  return(llr.w64);
2068 }
2069 
2070 __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
2071 {
2072  uint32_t result;
2073 
2074  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2075  return(result);
2076 }
2077 
2078 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
2079 {
2080  int32_t result;
2081 
2082  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2083  return(result);
2084 }
2085 
2086 __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
2087 {
2088  int32_t result;
2089 
2090  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2091  return(result);
2092 }
2093 
2094 #if 0
2095 #define __PKHBT(ARG1,ARG2,ARG3) \
2096 __extension__ \
2097 ({ \
2098  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
2099  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
2100  __RES; \
2101  })
2102 
2103 #define __PKHTB(ARG1,ARG2,ARG3) \
2104 __extension__ \
2105 ({ \
2106  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
2107  if (ARG3 == 0) \
2108  __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
2109  else \
2110  __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
2111  __RES; \
2112  })
2113 #endif
2114 
2115 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
2116  ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
2117 
2118 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
2119  ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
2120 
2121 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
2122 {
2123  int32_t result;
2124 
2125  __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
2126  return(result);
2127 }
2128 
2129 #endif /* (__ARM_FEATURE_DSP == 1) */
2130 
2133 #pragma GCC diagnostic pop
2134 
2135 #endif /* __CMSIS_GCC_H */
__set_FPSCR
__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
Set FPSCR.
Definition: cmsis_gcc.h:800
__ROR
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
Rotate Right in unsigned value (32 bit)
Definition: cmsis_gcc.h:962
__get_FPSCR
__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
Get FPSCR.
Definition: cmsis_gcc.h:774
__REV
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
Reverse byte order (32 bit)
Definition: cmsis_gcc.h:908
__enable_irq
__STATIC_FORCEINLINE void __enable_irq(void)
Enable IRQ Interrupts.
Definition: cmsis_gcc.h:135
__CLZ
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
Count leading zeros.
Definition: cmsis_gcc.h:1019
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:874
__REVSH
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
Reverse byte order (16 bit)
Definition: cmsis_gcc.h:942
__get_APSR
__STATIC_FORCEINLINE uint32_t __get_APSR(void)
Get APSR Register.
Definition: cmsis_gcc.h:227
__disable_irq
__STATIC_FORCEINLINE void __disable_irq(void)
Disable IRQ Interrupts.
Definition: cmsis_gcc.h:146
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:885
__DMB
__STATIC_FORCEINLINE void __DMB(void)
Data Memory Barrier.
Definition: cmsis_gcc.h:896
__get_CONTROL
__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
Get Control Register.
Definition: cmsis_gcc.h:157
__set_PSP
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
Set Process Stack Pointer.
Definition: cmsis_gcc.h:285
__USAT
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
Unsigned Saturate.
Definition: cmsis_gcc.h:1348
__get_IPSR
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
Get IPSR Register.
Definition: cmsis_gcc.h:213
__set_MSP
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
Set Main Stack Pointer.
Definition: cmsis_gcc.h:339
__REV16
__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
Reverse byte order (16 bit)
Definition: cmsis_gcc.h:927
__PACKED_STRUCT
#define __PACKED_STRUCT
Definition: cmsis_gcc.h:67
__SSAT
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
Signed Saturate.
Definition: cmsis_gcc.h:1323
__attribute__
Definition: suota.h:67
__get_xPSR
__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
Get xPSR Register.
Definition: cmsis_gcc.h:241
__get_PRIMASK
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
Get Priority Mask.
Definition: cmsis_gcc.h:390
__set_CONTROL
__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
Set Control Register.
Definition: cmsis_gcc.h:187
__set_PRIMASK
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
Set Priority Mask.
Definition: cmsis_gcc.h:420
__RBIT
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
Reverse bit order of value.
Definition: cmsis_gcc.h:989
__get_MSP
__STATIC_FORCEINLINE uint32_t __get_MSP(void)
Get Main Stack Pointer.
Definition: cmsis_gcc.h:309
__get_PSP
__STATIC_FORCEINLINE uint32_t __get_PSP(void)
Get Process Stack Pointer.
Definition: cmsis_gcc.h:255
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