概览

Double the drive of the standard 97U877 device. Low skew, low jitter PLL clock driver. 1 to 5 differential clock distribution (SSTL_18)

  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • Auto PD when input signal is at a certain logic state

文档

= 相关文档
类型 文档标题 日期
数据手册
97U2A845A Datasheet
PDF 313 KB
End Of Life Notice
PDN# : CQ-17-05 Quarterly Market Declined PDN
PDF 536 KB
2 items

设计和开发

ECAD 模块

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

扩展 ECAD 模块
Diagram of ECAD Models

产品选择

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    购买 / 样片
    器件号
    97U2A845AHLF
    circle过时
    memory
    view_in_ar
    		CABGA 28 C Yes Tray
    97U2A845AHLFT
    circle过时
    memory
    view_in_ar
    		CABGA 28 C Yes Reel
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