概览

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

  • Low skew, low jitter PLL clock driver
  • Max frequency supported = 400MHz (DDRII 800)
  • I2C for functional and output control
  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • Programmable skew through SMBus
  • Frequency defect control through SMBus
  • Individual output control programmable through SMBus

文档

设计和开发

ECAD 模块

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

扩展 ECAD 模块
Diagram of ECAD Models

产品选择

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    购买 / 样片
    器件号
    9P935AFLF
    circle过时
    memory
    view_in_ar
    		SSOP 28 C Yes Tube
    9P935AFLFT
    circle过时
    memory
    view_in_ar
    		SSOP 28 C Yes Reel
    9P935AGLF
    circle过时
    memory
    view_in_ar
    		TSSOP 28 C Yes Tube
    9P935AGLFT
    circle过时
    memory
    view_in_ar
    		TSSOP 28 C Yes Reel
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