概览
简介
Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.
特性
- 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
- Supports SSTL_18 JEDEC specification on data inputs and outputs
- Supports LVCMOS switching levels on CSR and RESET inputs
- Low voltage operation VDD = 1.7V to 1.9V
产品对比
应用
文档
= 相关文档
请登录后开启订阅
|
|
|
---|---|---|
类型 | 文档标题 | 日期 |
数据手册 | PDF 710 KB | |
End Of Life Notice | PDF 938 KB | |
End Of Life Notice | PDF 909 KB | |
产品变更通告 | PDF 113 KB | |
产品变更通告 | PDF 30 KB | |
产品变更通告 | PDF 398 KB | |
6 items
|
设计和开发
模型
ECAD 模块
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.