概览
描述
The 9FGV1008 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1008 provides one integer frequency, one copy of a fractional or spread spectrum output frequency, and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I2C bits allow easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I2C mode. Four unique I2C addresses are available, allowing easy I2C access to multiple components.
特性
-
PCIe Gen1–4 compliant
-
224fs RMS typical phase jitter at 156.25MHz (12kHz–20MHz)
-
2 programmable output pairs plus 1 LVCMOS REF output
-
1 integer and 1 fractional or spread-spectrum output per configuration
-
1MHz–325MHz integer outputs (LVDS or LP-HCSL)
-
1MHz–200MHz integer outputs (LVCMOS)
-
1.8V to 3.3V core VDD
-
Individual 1.8V to 3.3V VDDO for each programmable output pair
-
Supports HCSL, LVDS and LVCMOS I/O standards
-
Supports AC-coupled LVPECL and CML logic – see AN-891
-
3 × 3 mm 16-LGA packages with 50MHz integrated crystal option
-
Supported by Timing Commander™ software
文档
| 文档标题 | 类型 | 日期 | |
|---|---|---|---|
PDF390 KB
|
数据手册
|
||
PDF91 KB
|
应用文档
|
||
PDF1.16 MB
|
应用文档
|
||
PDF1.99 MB
|
应用文档
|
||
PDF256 KB
|
应用文档
|
||
PDF134 KB
|
应用文档
|
||
PDF222 KB
|
应用文档
|
||
PDF486 KB
|
应用文档
|
||
PDF255 KB
|
应用文档
|
||
PDF307 KB
|
应用文档
|
||
PDF480 KB
|
应用文档
|
||
PDF235 KB
|
应用文档
|
||
PDF1.90 MB
|
应用文档
|
||
PDF495 KB
|
应用文档
|
||
PDF442 KB
|
应用文档
|
||
PDF233 KB
|
应用文档
|
||
PDF160 KB
|
应用文档
|
||
PDF120 KB
|
应用文档
|
||
PDF565 KB
|
应用文档
|
||
PDF136 KB
|
应用文档
|
||
PDF144 KB
|
数据手册
|
||
PDF144 KB
|
数据手册
|
||
PDF401 KB
|
手册 - 软件
|
||
PDF507 KB
|
其他
|
||
PDF2.40 MB
|
概览
|
||
PDF129 KB
|
产品变更通告
|
||
PDF143 KB
|
产品变更通告
|
||
PDF1.35 MB
|
白皮书
|
设计和开发
软件与工具
开发板与套件
开发板与套件
Evaluation Kit for 9FGV1008 Programmable PhiClock™ Generator
This is the evaluation board for the 9FGV1008 programmable PhiClockTM generator. It provides a convenient way of configuring and programming the blank parts for the...
模型
ECAD 模块
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
产品选择
此为出厂可配置设备。试用自定义部件配置工具。
Processing table
器件号 |
Output Type |
Output Freq Range (MHz) |
Supply Voltage (V) |
Xtal Freq (MHz) |
Carrier Type |
购买 / 样片 |
|---|---|---|---|---|---|---|
| LP-HCSL, LVDS | 100, 125, 156.25 | 1.8, 3.3 | 50 | Tray | 获取样片, | |
| LP-HCSL, LVDS | 100, 125, 156.25 | 1.8, 3.3 | 50 | Reel | ||
| LP-HCSL, LVDS | 100, 125, 156.25 | 1.8, 3.3 | 50 | Tray | ||
| LP-HCSL, LVDS | 100, 125, 156.25 | 1.8, 3.3 | 50 | Reel |
Tips for Using This Parametric Table:
- Hide Filters button in header: Collapse or expands filters
- Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
- Reset button in header: Reset all filters to the page default
- Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
- Export button in header: Export the filtered results of the table to an Excel document
- Filter parts search bar in header: Type to filter table results by part number
- Hide column button in column headers: Select to hide columns in table
- AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
- Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
- Document icon next to product name in row: View the featured document for this product
- Chip icon next to the right of the document icon in row: View the block diagram for this product
- Cart icon to the right of the chip icon: Indicates that samples are available for this product
play_circle_filled视频和培训
PCIe Reference Clock Jitter Budgets
IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Video List
