概览

描述

The 72V51443 multi-queue flow-control device is a single chip within which between 1 and 16 discrete FIFO queues can be setup. All queues within the device have common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user.

特性

  • Total Available Memory = 1,179,648 bits
  • 166 MHz High speed operation (6ns cycle time)
  • 3.7ns access time
  • Available Memory in blocks of 512 x 18 or 1,024 x 9
  • Independent Read and Write access per queue
  • 100% Bus Utilization, Read and Write on every clock cycle
  • Global Bus Matching - (All Queues have same Input Bus Width and Output Bus Width)
  • User Selectable Bus Matching Options: - x18in to x18out - x9in to x18out - x18in to x9out - x9in to x9out
  • FWFT mode of operation on read port
  • JTAG Functionality (Boundary Scan)
  • Available in a 256-pin PBGA package
  • Industrial temperature range (-40C to +85C) is available

文档

文档标题 类型 日期
PDF486 KB
数据手册
PDF142 KB
应用文档
PDF167 KB
应用文档
PDF112 KB
应用文档
PDF217 KB
应用文档
TXT11 KB
应用文档
PDF24 KB
产品变更通告
PDF80 KB
产品变更通告
PDF38 KB
产品变更通告
PDF211 KB
产品变更通告
PDF26 KB
产品变更通告

设计和开发

模块

模块

Title Type Date
模型 - BSDL

支持