概览
描述
The 72V3614 is a 3.3V version of the 723614. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored.
特性
- Supports clock frequencies up to 83 MHz
- Fast access times of 8 ns
- Free-running CLKA and CLKB can be asynchronous or coincident
- Mailbox bypass Register for each FIFO
- Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word), and 9 bits (byte)
- Three modes of byte-order swapping on port B
- Programmable Almost-Full and Almost-Empty flags
- Passive parity checking on each port
- Available in 120-pin TQFP packages
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