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概览

描述

The CD4020BMS (14-stage), CD4024BMS (7-stage), and CD4040BMS (12-stage) are ripple carry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered. The CD4020BMS, CD4024BMS and CD4040BMS are supplied in these 14-lead outline packages: Braze Seal DIP H4W, H4Q and H4X; Frit Seal DIP H1F and H1B; and Ceramic Flatpack H6W and H3W.

特性

  • High-voltage types (20V rating)
  • Medium-speed operation
  • Fully static operation
  • Buffered inputs and outputs
  • 100% tested for quiescent current at 20V
  • Standardized symmetrical output characteristics
  • Common reset
  • 5V, 10V and 15V parametric ratings
  • Maximum input current of 1µa at 18V over full package temperature range:
    • 100nA at 18V and 25 °C
  • Noise margin (over full package temperature range):
    • 1V at VDD = 5V
    • 2V at VDD = 10V
    • 2.5V at VDD = 15V
  • Meets all requirements of JEDEC tentative standard No. 13B, "Standard Specifications For Description Of "B" Series CMOS devices

产品对比

应用

  • Control counters
  • Timers
  • Frequency dividers
  • Time-delay circuits

文档

类型 文档标题 日期
数据手册 PDF 578 KB
宣传手册 PDF 467 KB
EOL 通告 PDF 603 KB
涨价通告 PDF 360 KB
其他
产品咨询 PDF 499 KB
产品变更通告 PDF 230 KB
7 items

设计和开发

模型

ECAD 模块

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Diagram of ECAD Models

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