概览
描述
The M1026 is a Voltage Controlled SAW Oscillator (VCSO) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting up to 2.5Gb data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M1026 module includes a proprietary Surface Acoustic Wave (SAW) delay line as part of the VCSO. This results in a high-frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter.
特性
- Integrated SAW delay line
- Low phase jitter of < 0.5ps RMS, typical (12kHz to 20MHz)
- Output frequencies of 62.5MHz to 175MHz (Specify VCSO output frequency at time of order)
- LVPECL clock output (CML and LVDS options available)
- Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
- Loss of Lock (LOL) output pin
- Narrow bandwidth control input (NBW pin)
- AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure
- Acknowledge pin (REF_ACK pin) indicates the actively selected reference input
- Hitless Switching (HS) options with or without Phase Build-out (PBO) to enable SONET (GR-253) /SDH (G.813) MTIE and TDEV compliance during reselection
- Pin-selectable feedback and reference divider ratios
- Single 3.3V power supply
- Small 9mm x 9mm surface mount package
产品对比
应用
设计和开发
模型
ECAD 模块
点击产品选项表中的 CAD 模型链接，查找 SamacSys 中的原理图符号、PCB 焊盘布局和 3D CAD 模型。如果符号和模型不可用，可直接在 SamacSys 请求该符号或模型。
产品选项
当前筛选条件