瑞萨电子 (Renesas Electronics Corporation)
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9DB433

有效

4-Output 3.3V PCIe Gen1-2-3 Zero Delay/Fanout Buffer

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9DB433 Datasheet
注意 - 建议使用以下设备作为替代品：
9DBL0455 - 4-Output 3.3V PCIe Gen 1–7 Clock Fanout Buffer with LOS

概览

The 9DB433 zero delay buffer (ZDB) supports PCIe Gen3 requirements while being backward compatible with PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from a 932S421 or 932SQ420 or equivalent main clock generator.

  • Four 0.7V HCSL differential output pairs
  • Phase jitter: PCIe Gen3 < 1ps rms
  • Phase jitter: PCIe Gen2 < 3.1ps rms
  • Phase jitter: PCIe Gen1 < 86ps peak-to-peak
  • Supports Zero Delay Buffer mode and Fanout mode
  • Bandwidth programming available
  • 33MHz to 110MHz operation in PLL mode
  • 10MHz to 110MHz operation in Bypass mode

文档

设计和开发

ECAD 模块

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扩展 ECAD 模块
Diagram of ECAD Models

模型
类型 文档标题 日期
模型 - IBIS
9DB433A IBIS Model
ZIP 11 KB
1 item

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视频和培训

PCIe Clocking Architectures (Common and Separate)

This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

Watch the Video Series Below

Video List
PCIe Clocking Architectures (Common and Separate)
PCIe Common Clock Architecture and its Impact on Clocking
PCIe Separate Reference without Spread Clock Architecture
PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
Choosing the PLL Bandwidth for Zero Delay Buffers in PCIe Timing Systems

新闻和博客

Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System 博客 2022年4月14日
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications 博客 2018年5月22日
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices 新闻 2018年4月30日