FemtoClock™ 2 Evaluation Kit
This is the evaluation kit for the RC32514A and RC22514A. The board will come populated with an RC32514. The RC22514 is functionally a subset of the RC32514A, so this...
概览
描述
The RC22514A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs (max). The RC22514A can act as a frequency synthesizer to locally generate the reference clock or as a DCO for frequency margining or OTN clock applications, relying on an internal crystal reference source.
特性
- Jitter below 100fs RMS maximum (10kHz to 20MHz)
- PLL core consists of fractional-feedback Analog PLL (APLL)
- APLL frequency independent of input / crystal frequency
- Operates as a frequency synthesizer or Digitally Controlled Oscillator (DCO)
- DCO has tuning granularity of < 1ppb
- Programmable status output
- 4 differential / 8 LVCMOS outputs
- Any frequency from 10MHz to 1GHz (180MHz for LVCMOS)
- Programmable output buffer supports HCSL (DC-coupled), LVDS/LVPECL/CML (AC-coupled) or two LVCMOS
- Differential output swing is selectable: 400mV to 800mV
- Output clock phase individually adjustable in 100ps steps
- Output Enable input with programmable effect
- Supports up to 1MHz I2C or up to 20MHz SPI serial processor port
- Can configure itself automatically after reset via internal customer-definable One-Time Programmable (OTP) memory with up to four different configurations
- 4 × 4 mm 28-VFQFPN package
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设计和开发
软件与工具
软件与工具
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开发板与套件
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视频和培训
Lab on the Cloud Demo for FemtoClock®2 Ultra-Low Phase Noise Synthesizer and Jitter Attenuator
Demonstration of Renesas’ Lab on the Cloud virtual environment for FemtoClock®2 ultra-low phase noise synthesizer and jitter attenuator.
Video List
