概览
描述
The 723633 is a 512 x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers.
特性
- IDT Standard timing or First Word Fall Through Timing
- Programmable Almost-Empty and Almost-Full flags
- Serial or parallel programming of partial flags
- Big- or Little-Endian format for word and byte bus sizes
- Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings
- Easily expandable in width and depth
- Auto power down minimizes power dissipation
- Available in 128-pin TQFP package
产品对比
应用
设计和开发
模型
ECAD 模块
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