概览
描述
The 72V3643 is a 1K x 36 Sync FIFO that is a 3.3V version of the 723643. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. These devices can operate in the IDT Standard mode word or First Word Fall Through mode.
特性
- Clock frequencies up to 100 MHz (6.5 ns access time)
- Programmable Almost-Empty and Almost-Full flags
- Serial or parallel programming of partial flags
- Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)
- Big- or Little-Endian format for word and byte bus sizes
- Reset clears data and configures FIFO
- Partial Reset clears data but retains configuration settings
- Mailbox bypass registers for each FIFO
- Easily expandable in width and depth
- Auto power down minimizes power dissipation
- Available in 128-pin TQFP package
- Industrial temperature range (–40C to +85C) is available
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