时钟和时序

Renesas 的低抖动时钟发生器均是基于 PLL 的产品，因此可在一个应用中生成一个或多个时钟信号。 此类产品包含的低相位噪声振荡器适用于大多数串行数据应用。 这些低抖动时钟具有各种单端或差分信号级，如 LVCMOS、LVPECL、LVDS、HCSL、SSTL、HSTL 等。

一旦选定时钟发生器，便可使用低加性相位噪声扇出缓冲器来提供额外的拷贝和输出类型。 Renesas 拥有业内最广泛的低抖动时钟和低相位噪声振荡器产品系列，适用于各种高度优化的解决方案。 对于应用特定型低抖动时钟（如 PCIe、RF 和网络同步）。

（提示： 如果需要不止一个唯一的输出频率（如 100MHz 和 125MHz），可使用“输出库”参数选择器。 每个库与唯一的输出频率对应。 每个库的输出数量有很大差异，取决于器件。）

低抖动时钟/低相位噪声振荡器的主要参数

选择用于特定应用的低抖动时钟时，有许多重要的因素需要考虑。 用户可以下列参数作为起始点，来缩小潜在解决方案的范围：

  • 相位抖动：指在理想周期计时信号中不希望出现的偏差。 Renesas' 提供的低抖动时钟的 RMS 相位抖动通常低于 700fs，在某些高性能应用中甚至低于 300fs。
  • 输出频率范围：输出频率的有效范围。 Renesas 提供低相位噪声振荡器来满足所有主流应用的频率需求。
  • 输出类型：指低抖动时钟所需输出的信号类型。 Renesas 提供 CML、HCSL、HSTL、LVCMOS、LVDS、LVHSTL、LVPECL 和 LVTTL 等产品。
  • 核心电压：为低相位噪声振荡器供电的电源电压。 它通常由系统中可用的电源轨决定，并往往会对输出的电压电平产生影响。 Renesas’ 的低相位噪声时钟有 2.5V 和 3.3V 两个版本。

关于低抖动时钟（低相位噪声振荡器）
低抖动时钟是能够产生同步系统’操作所用计时信号的复杂 IC。 最基本的低抖动时钟由谐振电路和放大器组成。 所产生的计时信号涵盖范围从简单的 50% 占空比方波到更复杂的布置。 在此情况下，谐振电路通常是石英压电低相位噪声振荡器。 Renesas 提供多个系列的低抖动时钟，这些时钟具有不同级别的功率、性能和灵活性，几乎能满足需要低相位噪声振荡器的任何应用的需求。

产品选型表

    Processing table
    Outputs (#)
    Output Type
    Output Freq Range (MHz)
    Input Freq (MHz)
    Inputs (#)
    Input Type
    Output Banks (#)
    Core Voltage (V)
    Output Voltage (V)
    Phase Jitter Typ RMS (ps)
    Phase Jitter Max RMS (ps)
    105°C Max. Case Temp.
    器件号
    5L35021
    VersaClock® 3S Programmable Clock Generator    		 5 LP-HCSL, LVCMOS 0.032768 - 125 1 - 160 1 Crystal, HCSL, LVCMOS, LVDS, LVPECL 3 1.8 1.8 3
    5P35021
    VersaClock® 3S Programmable Clock Generator    		 5 LP-HCSL, LVCMOS, LVDS, LVPECL 0.032768 - 500 1 - 160 1 Crystal, LP-HCSL, LVCMOS, LVDS, LVPECL 3 3.3 1.8, 2.5, 3.3 3
    5P49V5913
    VersaClock® 5 Low Power Programmable Clock Generator    		 3 HCSL, LVCMOS, LVDS, LVPECL 1 - 350 1 - 350 2 Crystal, HCSL, LVCMOS, LVDS, LVPECL 2 1.8, 2.5, 3.3 1.8, 2.5, 3.3 0.7 1.5
    5P49V60
    VersaClock® 6E Programmable Clock Generator for Automotive    		 5 HCSL, LVCMOS, LVDS, LVPECL 1 - 350 1 - 350 2 Crystal, HCSL, LVCMOS, LVDS, LVPECL 4 1.8, 2.5, 3.3 1.8, 2.5, 3.3 0.5
    5P49V6901
    VersaClock® 6 Low Power Programmable Clock Generator    		 5 HCSL, LVCMOS, LVDS, LVPECL 1 - 350 1 - 350 2 Crystal, HCSL, LVCMOS, LVDS, LVPECL 4 1.8, 2.5, 3.3 1.8, 2.5, 3.3 0.5
    5P49V6913
    VersaClock® 6 Low Power Programmable Clock Generator    		 3 HCSL, LVCMOS, LVDS, LVPECL 1 - 350 1 - 350 2 Crystal, HCSL, LVCMOS, LVDS, LVPECL 2 1.8, 2.5, 3.3 1.8, 2.5, 3.3 0.5
    5P49V6914
    VersaClock® 6 Low Power Programmable Clock Generator    		 4 HCSL, LVCMOS, LVDS, LVPECL 1 - 350 1 - 350 2 Crystal, HCSL, LVCMOS, LVDS, LVPECL 3 1.8, 2.5, 3.3 1.8, 2.5, 3.3 0.5
    5P49V6965
    VersaClock® 6E Programmable Clock Generator    		 5 HCSL, LVCMOS, LVDS, LVPECL 1 - 350 1 - 350 2 Crystal, HCSL, LVCMOS, LVDS, LVPECL 4 1.8, 2.5, 3.3 1.8, 2.5, 3.3 0.5
    841N4830I
    FemtoClock™ NG Crystal-To-HCSL Frequency Synthesizer    		 6 HCSL, LVCMOS, LVPECL 25 - 100 25 2 Crystal, HCSL, LVDS, LVPECL 4 3.3 3.3 0.34
    8T49N240
    FemtoClock™ NG Universal Frequency Translator    		 4 HCSL, LVCMOS, LVDS, LVPECL 0.008 - 1000 0.008 - 875 2 HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL 4 2.5, 3.3 1.8, 2.5, 3.3 0.2
    8T49N241
    FemtoClock™ NG Universal Frequency Translator    		 4 HCSL, LVCMOS, LVDS, LVPECL 0.008 - 1000 0.008 - 875 2 HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL 4 2.5, 3.3 1.8, 2.5, 3.3 0.35
    8T49N366I
    FemtoClock NG Triple Universal Frequency Translator    		 6 LVDS, LVPECL 0.98 - 1300 0.008 - 710 7 HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL 3 2.5 2.5 0.333 0.465
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    VersaClock 5 Low Jitter Lab Demonstration

    Description:

    Lab demonstration and clock jitter measurement showing VersaClock 5. The frequency analyzer showing phase jitter at approximately 575 picoseconds RMS. Presented by Baljit Chandhoke, product manager at IDT. For more information about VersaClock, visit www.idt.com/go/VersaClock5

    Transcript:

    Hello, my name is Baljit Chandhoke, and I'm the Product Line Manager of timing products at IDT. Today, I will be giving you a brief lab demonstration of our new product, "VersaClock 5".

    VersaClock 5 is a low power clock generator, with best in class jitter performance of 0.7 psec. It has extremely low power with core current consumption of only 30 MA. It is extremely programmable, and you can get any frequency you want at the output, up to 350MHz.

    Now I'm going to start the lab demonstration. I have with me, an evaluation board. The evaluation board is powered by the USB cable, and is also used to control the VersaClock 5.

    This is the Timing Commander software, which controls the VersaClock 5 device. As you see, I have it configured for 125MHz, LVPECL output, on Output 1.

    On Output 2, I have it configured at 125MHz, HCSL output. Output 3, I have it configured at 156.25MHz LVDS, and Output 4 has 312.5MHz. All the outputs are operational and have different output frequencies.

    Now, let's take a look at the performance. With all these outputs operational, and on Output 1, which is operating at 125MHz, I see 575 fsec RMS phase jitter from 12K to 20MHz.

    This is industry leading in the power consumption of 30MA core in the space.

    Now let's change the frequency, and see what happens to the phase noise. I'm going to change the frequency on Output 1 to 100MHz.

    As you see, the frequency changed to 100MHz as shown on the screen, and the phase noise is still 576 fsec, from 12K to 20MHz. The noise floor is close to 150dBc.

    So this product maintains the great performance, across a wide range of frequencies, as well as across multiple output types, and with different frequencies of the output.

    So it provides you, a complete system solution, meeting the requirements of all your clocking needs in your system.

    Video List
    VersaClock 5 Low Jitter Lab Demonstration