概览
描述
The 71V65703 3.3V CMOS SRAM, organized as 256K x 36, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus it has been given the name ZBT™, or Zero Bus Turnaround. The 71V65703 contains address, data-in, and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.
特性
- High-performance system speed - 100MHz (7.5ns Clock-to-Data access)
- ZBT feature - No dead cycles between write and read cycles
- Internally synchronized output buffer enable eliminates the need to control OE
- Single R/W (Read/Write) control pin
- 4-word burst capability (interleaved or linear)
- Individual byte write (BW1 - BW4) control (May tie active)
- Three chip enables for simple depth expansion
- 3.3V power supply (±5%)
- 3.3V (±5%) I/O supply (VDDQ)
- Power down controlled by ZZ input
- Available in 100-pin TQFP, 119-pin BGA, and 165 fpBGA packages
产品对比
应用
设计和开发
模型
ECAD 模块
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