概览
描述
Provides 48 PCIe Gen3 lanes and 12 ports of high-performance, deterministic system interconnect switching. All ports receive full line rate, non-blocking throughput for multiple traffic flows regardless of switch loading.
特性
- 48 PCIe Gen3 Lanes, 12 Switch Ports
- Non-blocking switch architecture optimized for High Performance System Interconnect
- Partionable switch architecture for true multi-root support
- Internal buffering and flow control credits optimized for maximum bandwidth and large payloads
- Low latency, Low power
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应用
文档
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| 类型 | 文档标题 | 日期 |
| 数据手册 | PDF 368 KB | |
| EOL 通告 | PDF 720 KB | |
| EOL 通告 | PDF 647 KB | |
| EOL 通告 | PDF 898 KB | |
| 器件勘误表 | PDF 61 KB | |
| 手册 - 硬件 | PDF 2.83 MB | |
| 产品简述 | PDF 396 KB | |
| 应用说明 | PDF 351 KB | |
8 items
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设计和开发
软件与工具
开发板与套件
评估
Evaluation Board SDK for the 89H48H12G3
The 89KTPES48H12G3 Evaluation Board provides an evaluation platform for the 89H48H12G3 switch. The 89KTPES48H12G3 is a vehicle to test and evaluate the functionality of the 89H48H12G3 switch. Customers can use this board to get a headstart on software development prior to the arrival of their...
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