封装信息
| Lead Count (#) | 48 |
| Pkg. Code | DXG48 |
| Pitch (mm) | 0.5 |
| Pkg. Type | PTQFP |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 1.0 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
产品属性
| Lead Count (#) | 48 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 250 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range | 0 to 70°C |
| Core Voltage (V) | 3.3 |
| Divider Value | 1, 2, 3, 4, 5, 6, 8, 10 |
| Feedback Divider | 3 - 3, 4 - 4, 5 - 5, 6 - 6, 8 - 8, 10 - 10 |
| Feedback Input | No |
| Hitless Protection | Yes |
| Input Freq (MHz) | 49 - 213.3 |
| Input Type | LVPECL, LVDS, HSTL, SSTL, HCSL |
| Inputs (#) | 2 |
| Length (mm) | 7 |
| MOQ | 250 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 49 - 640 |
| Output Signaling | LVPECL |
| Output Skew (ps) | 100 |
| Output Type | LVPECL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 6 |
| Package Area (mm²) | 49.0 |
| Phase Jitter Typ RMS (ps) | 0.600 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 1.0 |
| Pkg. Type | PTQFP |
| Prog. Clock | No |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| VCO Max Freq (MHz) | 640 |
| VCO Min Freq (MHz) | 490 |
| Width (mm) | 7 |
描述
The 873996 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the HiPerClockS™ family of low jitter/phase noise devices from IDT. The 873996 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are critical. The device receives two differential LVPECL clock signals from which it generates 6 LVPECL clock outputs with "zero" delay. The output divider and feedback divider selections also allow for frequency multiplication or division.
The 873996 Dynamic Clock Switch (DCS) circuit continuously monitors both input clock signals. Upon detection of a failure (input clock stuck LOW or HIGH for at least 1 period), INP_BAD for that clock will be set HIGH. If that clock is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance.
The low jitter characteristics combined with input clock monitoring and automatic switching from bad to good input clocks make the 873996 an ideal choice for mission critical applications that utilize 1G or 10G Ethernet or 1G/4G/10G Fibre Channel.