瑞萨电子 (Renesas Electronics Corporation)
搜索

82P33741

有效

Port Synchronizer for IEEE 1588 and 10G/40G Synchronous Ethernet

立即订购
82P33741 Datasheet

概览

The 82P33741 Port Synchronizer for IEEE 1588 and 10G/40G Synchronous Ethernet provides tools to manage timing references, clock conversion and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE). The device supports up to three independent timing paths for: IEEE 1588 clock generation; SyncE clock generation; and general purpose frequency translation. The device outputs low-jitter clocks that can directly synchronize 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

► Download the Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 white paper

82P33741 Functional Block Diagram
82P33741 Functional Block Diagram
  • Supports 3 independent timing paths: IEEE 1588, physical layer (SyncE, SONET/SDH, PDH, CPRI/OBSAI) and recovered line clock
  • Phase synchronizes IEEE 1588 TSUs (Time Stamp Units) at network ports with redundant system-wide IEEE 1588 clock and sync pulse pairs: 1PPS (Pulse Per Second) sync pulses
  • Precise 1PPS edge alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
  • Frequency synchronizes physical layer ports with redundant system-wide frequency references
  • Generates clocks for: 10GBASE-R, 10GBASE-W, 40GBASE-R and CPRI/OBSAI interfaces without external jitter attenuators: jitter generation <0.3 ps RMS (10 kHz to 20 MHz)
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • Prevents time errors and PHY bit errors with automatic reference switching, optional hitless reference switching and revertive or non-revertive reference switching
  • DPLLs lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI/OBSAI and GNSS frequencies using fractional-N input dividers
  • Automatically loads configuration from an external EPROM after reset without processor intervention
  • 144 pin CABGA package

文档

设计和开发

82EBP33831 Evaluation Board - top view

82EBP33831

Evaluation
了解更多

Evaluation Board for 82P33831 Synchronization Management Unit for IEEE 1588 and 10G/40G Synchronous Ethernet

The 82EBP33831 Evaluation board for IEEE 1588 and Synchronous Ethernet (SyncE) allows the user to connect up to eight differential-ended, up to eight single-ended, and...

特色文件:
82EBP33831 Evaluation Board User Guide

ECAD 模块

点击产品选项表中的 CAD 模型链接，查找 SamacSys 中的原理图符号、PCB 焊盘布局和 3D CAD 模型。如果符号和模型不可用，可直接在 SamacSys 请求该符号或模型。

扩展 ECAD 模块
Diagram of ECAD Models

模型
类型 文档标题 日期
模型 - BSDL
82P33741 BSDL
BSD 20 KB
模型 - IBIS
82P33741 IBIS
IBS 1.04 MB
2 items

产品选项

当前筛选条件