概览
简介
The 8A34046 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) and Optical Transport Network (OTN) is a highly integrated timing device with four Digital PLL (DPLL) channels and four Digitally Controlled Oscillator (DCO) channels. The device integrates the timing blocks necessary to implement the SETS function as described in ITU-T G.8264.
The 8A34046 DPLL channels can be configured to comply with ITU-T G.8262 and G.8262.1 or as jitter attenuators; they can also be configured as DCOs. The DCO channels can be connected to a DPLL channel to supply additional outputs and frequencies for that DPLL; alternatively, they can be controlled by external software or they can free run based on the local oscillator. The device can be used as a single timing and synchronization source for a system or two of these devices can be used as a redundant pair for improved system reliability. Input-to-input, input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs ultra-low jitter clocks that can directly synchronize SerDes running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH, and PDH interfaces.
To see other devices in this product family, visit the ClockMatrix Timing Solutions page.
特性
- Four independent Digital PLLs (DPLLs) and four independent Digitally Controlled Oscillators (DCOs)
- DPLLs comply with ITU-T G.8262 and G.8262.1 for SyncE and OTN
- DPLLs lock to any frequency from 1kHz to 1GHz
- DPLLs/DCOs generate any frequency from 0.5Hz to 1GHz
- Jitter output below 150fs RMS (typical)
- Supports up to 4 differential; or 8 single-ended reference clock inputs
- Supports up to 12 differential outputs; or 24 LVCMOS outputs
- Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring, and/or LOS input pins
- Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive/non-revertive and other programmable settings
- Serial processor ports support 1MHz I²C or 50MHz SPI
- The device can configure itself automatically after reset via:
- Internal customer-programmable one-time programmable memory
- Standard external I²C EPROM via separate I²C Master Port
产品对比
应用
- Core and access IP switches/routers
- Synchronous Ethernet equipment
- 10Gb, 40Gb, and 100Gb Ethernet interfaces
- Wireless infrastructure for 4.5G and 5G network equipment
- OTN muxponders and line cards
设计和开发
软件与工具
软件与工具
| Software title
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Software type
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公司
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|---|---|---|
| Timing Commander Timing Commander™ 是一个基于 Windows™ 的创新软件平台，通过这个平台，系统设计工程师可以通过直观且灵活的图形用户界面 (GUI) 对精密的计时设备进行配置、编程和监控。
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Code Generator | 瑞萨电子 |
1 item
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模型
ECAD 模块
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| 0 to 70°C | Tray | 3 | 获取样片, | ||
| 0 to 70°C | Reel | 3 | |||
| 0 to 70°C | Reel | 3 |
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视频和培训
IDT ClockMatrix™ 8A3404x Multi-channel DPLL / DCO Programmable, Sub-150fs Jitter Timing Solution
The ClockMatrix family of devices offers high-performance, precision timing solutions for applications with up to 100 Gbps interface speeds. They are versatile in their usage, supporting functions such as clock generation, frequency translation, jitter attenuation, and phase alignment across a range of densities. The 8A3404x Multichannel Digital PLL/DCO family manages timing references and clock conversion for protocols like SyncE, OTN, and CPRI. It features multiple independent timing channels for clock generation, jitter attenuation, and universal frequency translation, outputting ultra-low-jitter clocks for high-speed interfaces like SERDES, CPRI/OBSAI, SONET/SDH, and PDH.
Related Resources
Video List
