瑞萨电子 (Renesas Electronics Corporation)
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9DB436

过时

4-Output 3.3V HCSL PCIe Buffer

9DB436 Datasheet

概览

The 9DB436 is a zero delay/fanout buffer for PCI Express™ clocking. It supports PCIe Gen 1–3 in zero delay mode and PCIe Gen 1–4 in fanout mode. The 9DB436 also features a Safe Power Sequence (SPS) clock input. The 9DB436 is a pin-compatible upgrade to the 9DB433 and 9DB434.

9DB436 - Block Diagram
9DB436 - Pinout
9DB436 - Safe Power Sequence Clock Input Diagram
9DB436 - Block Diagram
9DB436 - Pinout
9DB436 - Safe Power Sequence Clock Input Diagram
  • Four 0.7V current-mode differential HCSL output pairs
  • PCIe Gen 3 jitter < 0.6ps RMS in ZDB mode
  • PCIe Gen 4 additive jitter < 0.1ps RMS in fanout mode
  • SPS internal receiver bias network keeps the input clock parked when input is floating
  • Supports both 85Ω and 100Ω output impedance with appropriate resistor selection
  • OE# pins default to controlling outputs
  • Supports zero delay buffer mode and fanout mode
  • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
  • Spread spectrum compatible
  • Three selectable SMBus addresses

文档

设计和开发

ECAD 模块

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Diagram of ECAD Models

模型
类型 文档标题 日期
模型 - IBIS
9DB436 IBIS Model
ZIP 12 KB
1 item

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视频和培训

PCIe Clocking Architectures (Common and Separate)

This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

Watch the Video Series Below

Video List
PCIe Clocking Architectures (Common and Separate)
PCIe Common Clock Architecture and its Impact on Clocking
PCIe Separate Reference without Spread Clock Architecture
PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
Choosing the PLL Bandwidth for Zero Delay Buffers in PCIe Timing Systems

新闻和博客

Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System 博客 2022年4月14日
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications 博客 2018年5月22日
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices 新闻 2018年4月30日