RZ/N2H 评估板套件
RZ/N2H 评估板套件是用于 RZ/N2H MPU 的一款评测和开发套件。 由于它具有板载仿真器，您只需将附带连线接到 PC 即可开始评测。 该评测板包含千兆以太网 PHY、非易失性存储器和 LPDDR4 存储器等功能丰富的元件，无需扩展板即可评估 RZ/N2H 的各种功能。
此外，通过扩展逆变器板，还可以实现多轴电机控制。
概览
描述
The 9FGV0441 is a 4-output very-low power clock generator for PCIe Gen 1–4 applications with integrated output terminations providing Zo = 100Ω. The device has four output enables for clock management and supports two different spread spectrum levels in addition to spread off.
特性
- Integrated terminations provide 100Ω differential Zo; reduced component count and board space
- 1.8V operation; reduced power consumption
- OE# pins; support DIF power management
- LP-HCSL differential clock outputs; reduced power and board space
- Programmable slew rate for each output; allows tuning for various line lengths
- Programmable output amplitude; allows tuning for various application environments
- DIF outputs are blocked until PLL is locked; clean system start-up
- Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
- External 25MHz crystal; supports tight ppm with 0ppm synthesis error
- Configuration can be accomplished with strapping pins; SMBus interface is not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space saving 5mm x 5mm 32-VFQFPN; minimal board space
- Selectable SMBus addresses; multiple devices can easily share an SMBus segment
产品对比
应用
设计和开发
开发板与套件
模型
ECAD 模块
点击产品选项表中的产品，查找 SamacSys 中的原理图符号、PCB 足迹和 3D CAD 模型。点击产品选项表中的产品，查找 SamacSys 中的原理图符号、PCB 足迹和 3D CAD 模型。
产品选项
当前筛选条件
视频和培训
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
Video List
