概览
描述
The 9FGV1004 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1004 provides 1 copy each of 2 integer-related frequencies, 2 copies of a fractional or spread-spectrum frequency and 2 copies of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.
特性
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PCIe Gen1–4 compliant
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267fs RMS typical phase jitter at 156.25MHz (12kHz–20MHz)
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4 programmable output pairs plus 2 LVCMOS REF outputs
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2 integer and 1 fractional or spread-spectrum output per configuration
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1MHz–325MHz integer outputs (LVDS or LP-HCSL)
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1MHz–200MHz integer outputs (LVCMOS
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1.8V to 3.3V core VDD
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Individual 1.8V to 3.3V VDDO for each programmable output pair
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Supports HCSL, LVDS and LVCMOS I/O standards
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Supports AC-coupled LVPECL and CML logic – see AN-891
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4 × 4 mm 24-VFQFPN and 24-LGA packages with 50MHz integrated crystal option
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Supported by Timing Commander™ software
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视频和培训
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
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