瑞萨电子 (Renesas Electronics Corporation)
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553S

有效

Low Skew 1 to 4 Clock Buffer

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553S Datasheet

概览

The 553S is a low skew, single input to four output, LVCMOS clock buffer that offers a best-in-class additive phase jitter of sub 50fs.

553S Block Diagram
553S Pinout - DFN
553S Pinout - SOIC
553S Block Diagram
553S Pinout - DFN
553S Pinout - SOIC
  • Low additive phase jitter RMS: 50fs
  • Extremely low skew outputs (50ps)
  • Low-cost clock buffer
  • Packaged in 8-pin SOIC and small 8-pin DFN packages, Pb-free
  • Input/Output clock frequency up to 200MHz
  • Ideal for networking clocks
  • Operating voltages: 1.8V to 3.3V
  • Output Enable mode tri-state outputs
  • Advanced, low-power CMOS process
  • Extended temperature range: -40 °C to +105 °C

文档

相关文档
类型 文档标题 日期
数据手册
553S Datasheet
PDF 316 KB
应用笔记
Termination Options for High-Speed LVCMOS Driver Clock Drivers
PDF 187 KB
概览
Clock Distribution Overview
PDF 217 KB
产品变更通告
PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets
PDF 268 KB
产品变更通告
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly
PDF 611 KB
产品变更通告
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly
PDF 611 KB
应用笔记
AN-842 Thermal Considerations in Package Design and Selection
PDF 495 KB
应用笔记
AN-840 Jitter Specifications for Timing Signals
PDF 442 KB
应用笔记
AN-815 Understanding Jitter Units
PDF 565 KB
9 items

设计和开发

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视频和培训

Low-jitter LVCMOS Fanout Clock Buffers by IDT

This video overviews the LVCMOS Fanout Buffers, showcasing their best-in-class performance with extremely low phase jitter, minimal output skew, and low power consumption, along with other competitive features.

Video List
Low-jitter LVCMOS Fanout Clock Buffers by IDT

新闻和博客

IDT Introduces Ultra-Low-Jitter Family of LVCMOS Clock Buffers 新闻 2015年3月30日