瑞萨电子 (Renesas Electronics Corporation)
搜索

5P83905

有效

1.8V to 3.3V 1:6 Crystal Input to LVCMOS Output High-Performance Clock Fanout Buffer with OE

立即订购
5P8390x Datasheet

概览

The 5P83905 is a high-performance, 1-to-6 crystal input to LVCMOS fanout buffer with Output Enable (OE) pins. This device accepts a fundamental mode crystal from 10MHz to 40MHz and outputs LVCMOS clocks with best-in-class phase noise performance.

The 5P83905 features a synchronous glitch-free Output Enable function to eliminate any intermediate incorrect output clock cycles when enabling or disabling outputs. It comes in standard TSSOP packages or small QFN packages and can operate from 1.8V to 3.3V supplies.

5P83905 Block Diagram
5P83905 Pinout
5P83905 Block Diagram
5P83905 Pinout
  • Six copies of LVCMOS output clocks with best-in-class phase noise performance
  • Phase noise:
    Offset noise power (3.3V)
    • 100Hz: -131dBc/Hz
    • 1KHz: -145dBc/Hz
    • 10KHz: -154dBc/Hz
    • 100KHz: -161dBc/Hz
  • Operating power supply modes:
    • Full 3.3V, 2.5V, 1.8V
    • Mixed 3.3V core/2.5V output operating supply
    • Mixed 3.3V core/1.8V output operating supply
    • Mixed 2.5V core/1.8V output operating supply
  • Crystal oscillator interface
  • Synchronous Output Enable
  • Packaged in 16-pin TSSOP and QFN packages
  • Extended temperature range (-40 °C to +105 °C)

文档

相关文档
类型 文档标题 日期
数据手册
5P8390x Datasheet
PDF 459 KB
应用说明
Termination Options for High-Speed LVCMOS Driver Clock Drivers
PDF 187 KB
概览
Clock Distribution Overview
PDF 217 KB
产品变更通告
PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets
PDF 268 KB
概览
IDT Ultra-Low-Jitter Single-Ended Buffer Family Overview
PDF 252 KB
应用说明
AN-842 Thermal Considerations in Package Design and Selection
PDF 495 KB
应用说明
AN-840 Jitter Specifications for Timing Signals
PDF 442 KB
应用说明
AN-815 Understanding Jitter Units
PDF 565 KB
8 items

设计和开发

ECAD 模块

点击产品选项表中的 CAD 模型链接，查找 SamacSys 中的原理图符号、PCB 焊盘布局和 3D CAD 模型。如果符号和模型不可用，可直接在 SamacSys 请求该符号或模型。

扩展 ECAD 模块
Diagram of ECAD Models

模型
类型 文档标题 日期
模型 - IBIS
5P8390x IBIS Model
ZIP 25 KB
1 item

产品选项

当前筛选条件

视频和培训

5PB11xx Ultra Low Jitter LVCMOS Buffers

This video provides an overview of the LVCMOS High Performance Clock Buffer Family, highlighting their key features and capabilities.

Related Resources

Video List
5PB11xx Ultra Low Jitter LVCMOS Buffers
Low-jitter LVCMOS Fanout Clock Buffers by IDT

新闻和博客

IDT Introduces Ultra-Low-Jitter Family of LVCMOS Clock Buffers 新闻 2015年3月30日