瑞萨电子 (Renesas Electronics Corporation)
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74FCT38075S

有效

Low Skew 1 to 5 Clock Buffer

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74FCT38075S Datasheet

概览

The 74FCT38075S is a low skew, single input to five output, LVCMOS clock buffer that offers a best-in-class additive phase jitter of sub 50fs.

74FCT38075S Block Diagram
74FCT38075S Pinout - DFN
74FCT38075S Pinout - SOIC
74FCT38075S Block Diagram
74FCT38075S Pinout - DFN
74FCT38075S Pinout - SOIC
  • Extremely low RMS additive phase jitter: 50fs
  • Low output skew: 50ps
  • Packaged in an 8-pin SOIC and 8-pin DFN
  • Pb (lead) free package
  • Low-power CMOS technology
  • Operating voltages of 1.8 V to 3.3 V
  • Extended temperature range: -40 °C to +105 °C

文档

相关文档
类型 文档标题 日期
数据手册
74FCT38075S Datasheet
PDF 207 KB
应用笔记
Termination Options for High-Speed LVCMOS Driver Clock Drivers
PDF 187 KB
概览
Clock Distribution Overview
PDF 217 KB
产品变更通告
PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets
PDF 268 KB
产品变更通告
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly
PDF 611 KB
产品变更通告
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly
PDF 611 KB
应用笔记
AN-842 Thermal Considerations in Package Design and Selection
PDF 495 KB
应用笔记
AN-840 Jitter Specifications for Timing Signals
PDF 442 KB
应用笔记
AN-815 Understanding Jitter Units
PDF 565 KB
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视频和培训

Low-jitter LVCMOS Fanout Clock Buffers by IDT

This video overviews the LVCMOS Fanout Buffers, showcasing their best-in-class performance with extremely low phase jitter, minimal output skew, and low power consumption, along with other competitive features.

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Low-jitter LVCMOS Fanout Clock Buffers by IDT