封装信息
| Lead Count (#) | 36 |
| Pkg. Type | CLCC |
| Pkg. Code | CG36 |
| Pitch (mm) | 0.6 |
| Pkg. Dimensions (mm) | 9.0 x 9.0 x 2.8 |
环境和出口类别
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390000 |
| Moisture Sensitivity Level (MSL) | 1 |
产品属性
| Pkg. Type | CLCC |
| Lead Count (#) | 36 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| Abs. Pull Range Min. (± PPM) | 50 |
| Core Voltage (V) | 3.3 |
| Feedback Input | No |
| Input Freq (MHz) | 10 - 700 |
| Input Type | LVCMOS, LVPECL, LVDS |
| Inputs (#) | 2 |
| Length (mm) | 9 |
| MOQ | 57 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 19.44 - 19.44, 77.76 - 77.76, 155.52 - 155.52, 622.08 - 622.08 |
| Output Type | LVPECL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 81.0 |
| Pb Free Category | e4 Au |
| Phase Jitter Max RMS (ps) | 0.500 |
| Phase Jitter Typ RMS (ps) | 0.250 |
| Pitch (mm) | 0.6 |
| Pkg. Dimensions (mm) | 9.0 x 9.0 x 2.8 |
| Prog. Clock | No |
| Qty. per Carrier (#) | 54 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range | -40 to +85°C |
| Thickness (mm) | 2.8 |
| Width (mm) | 9 |
描述
The M2060/61/62 and M2065/66/67 are Voltage Controlled SAW Oscillator (VCSO) based clock PLLs designed for FEC clock ratio translation in 10Gb optical systems such as OC-192 or 10GbE. They support Forward Error Correction (FEC) clock multiplication ratios, and both forward (mapping) and inverse (de-mapping). Multiplication ratios are pin-selected from pre-programming look-up tables.