概览
描述
The 71V3577 3.3V CMOS SRAM is organized as 128K x 36 and contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.
特性
- Fast access times - 7.5ns up to 117MHz clock frequency
- LBO input selects interleaved or linear burst mode
- Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx)
- 3.3V core power supply
- Power down controlled by ZZ input
- 3.3V I/O
- Optional - Boundary Scan JTAG interface (IEEE 1149.1 compliant)
- Available in 100-pin TQFP, 119-pin BGA, and 165 fpBGA packages
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应用
设计和开发
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