封装信息
| Pkg. Type | LBGA |
| Pkg. Code | pkg_10375 |
| Lead Count (#) | 165 |
| Pkg. Dimensions (mm) | 15 x 13 x 1.46 |
环境和出口类别
| ECCN (US) | 5A002 |
| RoHS (UPD46365084BF1-E40-EQ1-A) | 英语日文 |
| Moisture Sensitivity Level (MSL) | |
| Pb (Lead) Free | Yes |
| HTS (US) |
产品属性
| Pkg. Type | LBGA |
| Carrier Type | Tray |
| Architecture | QDR-II |
| Burst Length (Words) | 4 |
| Data Width (bits) | 8 |
| Density (Kb) | 36000 |
| Frequency (Max) (MHz) | 250 |
| Lead Compliant | Yes |
| Lead Count (#) | 165 |
| Length (mm) | 15 |
| MIN Frequency (MHz) | 120 |
| MOQ | 1 |
| Pb (Lead) Free | Yes |
| Pkg. Dimensions (mm) | 15 x 13 x 1.46 |
| Read Latency (Clock) | 1.5 |
| Replacement Product | |
| Tape & Reel | No |
| Thickness (mm) | 1.46 |
| Width (mm) | 13 |
描述
Support is limited to customers who have already adopted these products.
DDR II / II+ (Double Data Rate) SRAMs and QDR^(TM) II / II+ (Quad Data Rate) SRAMs are the ideal memory devices for next generation networking and communications systems. These ultra-fast devices can support high bandwidth systems that require memories capable of very high operating frequencies combined with low latencies and full cycle utilization. DDR SRAMs can provide double data rate (DDR) operation on each data pin in write or read cycles, thus the data is written or read twice every clock cycle. This provides for a significantly higher transfer rate than standard synchronous SRAM devices. In applications that require continuous read/write capability such as in look-up tables for network switches and routers, DDR SRAMs are an ideal solution. QDR SRAMs can provide double data rate (DDR) operation on each data pin through independently operated read and write ports, and can transfer four words of data on one clock cycle. This allows for bus contention to be virtually eliminated between the memory controller and the SRAM. The QDR SRAMs can support high end network switches, routers and other communication solutions. 。