概览

描述

The 8A34045 Multichannel Digital PLL / Digitally Controlled Oscillator (DPLL/DCO) provides tools to manage timing references, clock conversion and timing paths for common communications protocols such as: Synchronous Ethernet (SyncE), Optical Transport Network (OTN) and Common Public Radio Interface (CPRI). The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for: clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.

特性

  • Four independent Digital PLLs (DPLLs)
  • Four independent Digitally Controlled Oscillators (DCOs)
  • Jitter output below 150fs RMS (typical)
  • DPLLs lock to any frequency from 1kHz to 1GHz
  • DPLLs / DCOs generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • Supports up to 4 differential or 8 single-ended reference clock inputs
  • Supports up to 12 differential outputs or 24 LVCMOS outputs
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • Optional XO_DPLL input allows a wider range for XO, TCXO or OCXO frequencies from 1MHz to 150MHz for applications that require a local oscillator with high stability
  • Serial processor ports support 1MHz I2C or 50MHz SPI
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory 
    • Standard external I2C EPROM via separate I2C Master Port

应用

文档

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器件勘误表
PDF10.53 MB
指南
PDF2.35 MB
指南
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指南
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指南
PDF5.61 MB
手册 - 硬件
XLSX321 KB
其他
PDF320 KB
概览
PDF135 KB
产品变更通告
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产品变更通告
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产品变更通告
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产品变更通告
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产品变更通告
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Release Note
PDF98 KB
原理图

设计和开发

软件与工具

软件下载

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模块

模块

Title Type Date
模型 - BSDL
模型 - IBIS

视频和培训

IDT ClockMatrix™ 8A3404x Multi-channel DPLL / DCO Programmable, Sub-150fs Jitter Timing Solution

The ClockMatrix family of devices are high-performance, precision timing solutions designed to simplify clock designs for applications with up to 100 Gbps interface speeds. They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation and phase alignment. A range of devices in the family support BBU, OTN, SyncE, synthesizer and jitter attenuator applications with several density options for each.

The 8A3404x Multichannel Digital PLL / Digitally Controlled Oscillator (DPLL/DCO) family provides tools to manage timing references, clock conversion and timing paths for common communications protocols such as: Synchronous Ethernet (SyncE), Optical Transport Network (OTN) and Common Public Radio Interface (CPRI).  The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources. 

The device supports multiple independent timing channels for: clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces

For more information, visit www.idt.com/clockmatrix.