Octal Transparent Latches (with 3-state outputs)
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概览
简介
When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
特性
- High-Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF)
- High Output Current: Fanout of 15 LSTTL Loads
- Wide Operating Voltage: VCC = 2 to 6 V
- Low Input Current: 1 µA max
- Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
文档
| Document title | Document type
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日期 日期 | |
|---|---|---|---|
| PDF 295 KB | 数据手册 | ||
| PDF 5.23 MB | 手册 | ||
| PDF 1.32 MB | 手册 | ||
| PDF 155 KB 日文 | 数据手册 | ||
| PDF 4.86 MB 日文 | 产品变更通告 | ||
| PDF 3.74 MB 日文 | 产品变更通告 | ||
| PDF 1.46 MB 日文 | 产品变更通告 | ||
| PDF 3.28 MB | 手册 | ||
| PDF 3.91 MB | 手册 | ||
| PDF 7.03 MB | 手册 | ||
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设计和开发
模型
ECAD 模块
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