概览
描述
The HXC44200 is a bi-directional dual channel PAM-4 CDR/Retimer. It supports a transmission data rate of 56Gbps PAM4 and 28Gbps NRZ. The HXC44200 can be used in a 50G SFP56 form factor and other small form factor modules. The device is optimized for Ethernet application. It is in full compliance with OIF CEI-56G-VSR and CEI-56G-MR. The total power consumption of the HXC44200 is below 700mW.
The HXC44200 has built-in programmable and adaptive equalization in both the receiver and the transmitter paths to compensate for transmission line losses and inter-symbol interference.
Auto DC-offset calibration is implemented with auto phase calibration and the unique CDR / Retimer architecture enables independent receive and transmit CDR loop bandwidth optimization for increased Jitter Tolerance and reduced Jitter Transfer performance.
The chip has a built-in, single 14GHz master VCO providing the oscillator output for each channel. In addition, the self-test functions, such as a PRBS generator / checker, Jitter Tolerance, and Eye Open Monitor, provide designers and users with module-level diagnostics and function tests.
The HXC44200 also integrates a CPU for programmable control, which could reduce BOM cost and enable better module design. I2C interface is used to control the built-in CPU.
特性
- Single chip 56Gbps CDR/Retimer with transmit and receiver
- Supports 56Gbps PAM-4 and 28Gbps NRZ
- Output swing up to 850mVpp
- 7-bit resolution for programmable and adaptive CTLE up to 7 dB equalization n receiver
- Programmable 3-tap de-emphasis for a transmit
- Linearity compensation for output through a look-up table
- Independent, adaptive bandwidth control in RX CDR for optimum jitter tolerance
- Internal and automatic DC and phase offset calibrations
- Reference-less and Master channel-less operation
- On-chip testability: EOM, JTOL, PRBS generator/checker, user-defined pattern generator
- Embedded CPU with RAM/ROM and downloadable firmware
- I2C control interface (16-bit address and data)
产品对比
应用
设计和开发
模型
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