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10Base-T/100Base-TX Integrated PHYceiver™ with RMII Interface

封装信息

Lead Count (#) 40
Pkg. Code NLG40
Pitch (mm) 0.5
Pkg. Type VFQFPN
Pkg. Dimensions (mm) 6.0 x 6.0 x 0.9

环境和出口类别

Moisture Sensitivity Level (MSL) 3
Pb (Lead) Free Yes
ECCN (US) NLR
HTS (US) 8542390001

产品属性

Lead Count (#) 40
Carrier Type Reel
Moisture Sensitivity Level (MSL) 3
Qty. per Reel (#) 5000
Qty. per Carrier (#) 0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range -40 to 85°C
Country of Assembly Taiwan
Country of Wafer Fabrication Taiwan, United States
Core Voltage (V) 3.3
Input Freq (MHz) 0 - 0
Length (mm) 6
MOQ 5000
Package Area (mm²) 36.0
Pitch (mm) 0.5
Pkg. Dimensions (mm) 6.0 x 6.0 x 0.9
Pkg. Type VFQFPN
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel Yes
Thickness (mm) 0.9
Width (mm) 6
Xtal Freq (KHz) 25 - 25
Xtal Inputs (#) 1

描述

The IDT1894-40 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC 8802-3. The IDT1894-40 is intended for MII, Node applications that require the Auto-MDIX feature that automatically corrects crossover errors in plant wiring. The IDT1894-40 incorporates Digital-Signal Processing (DSP) control in its Physical-Medium Dependent (PMD) sub layer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess of 24 dB at 100MHz. With this IDT-patented technology, the IDT1894-40 can virtually eliminate errors from killer packets. The IDT1894-40 provides a Serial-Management Interface for exchanging command and status information with a Station-Management (STA) entity. The IDT1894-40 Media-Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 Mb/s or 100Mb/s. In addition, the IDT1894-40 includes a programmable interrupt output function. This function consists of a digital output pin, an interrupt control register, a set of interrupt status register bits and a corresponding set of interrupt enable bits, and a pre-defined set of events which can be assigned as one of the interrupt sources. The purpose of this function is to notify the host of this PHY device when certain event happens via interrupt (the logic level on interrupt output pin going low or going high) instead of polling by the host. The events that could be used to generate interrupts are: receiver error, Jabber, page received, parallel detect fault, link partner acknowledge, link status change, auto-negotiation complete, remote fault, collision, etc. Applications: NIC cards, PC motherboards, switches, routers, DSL and cable modems, game machines, printers, network connected appliances, and industrial equipment.