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Clock Slicer User Configurable PECL Input Zero Delay Buffer

封装信息

Pkg. Type: QSOP
Pkg. Code: PCG28
Lead Count (#): 28
Pkg. Dimensions (mm): 9.9 x 3.8 x 1.47
Pitch (mm): 0.64

环境和出口类别

Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090
Moisture Sensitivity Level (MSL) 1

产品属性

Pkg. Type QSOP
Lead Count (#) 28
Pb (Lead) Free Yes
Carrier Type Reel
Advanced Features Feedback Input
Core Voltage (V) 3.3
Feedback Input Yes
Input Freq (MHz) 1.5 - 200
Input Type LVPECL
Inputs (#) 1
Length (mm) 9.9
MOQ 2500
Moisture Sensitivity Level (MSL) 1
Output Banks (#) 2
Output Freq Range (MHz) 4 - 140
Output Skew (ps) 250
Output Type LVCMOS
Output Voltage (V) 3.3
Outputs (#) 2
Package Area (mm²) 37.6
Pb Free Category e3 Sn
Period Jitter Typ P-P (ps) 90.000
Pitch (mm) 0.64
Pkg. Dimensions (mm) 9.9 x 3.8 x 1.47
Prog. Clock No
Qty. per Carrier (#) 0
Qty. per Reel (#) 2500
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel Yes
Temp. Range (°C) -40 to 85°C
Thickness (mm) 1.47
Width (mm) 3.8
已发布 No

描述

The 527-02 Clock Slicer is the most flexible way to generate a CMOS output clock from a PECL input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. A SYNC pulse indicates when the rising clock edges are aligned with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The 527-02 aligns rising edges on PECLIN with FBIN at a ratio determined by the reference and feedback dividers. For a PECL input and output clock with zero delay, use the 527-04. For a CMOS input and PECL output with zero delay, use the 527-03.